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Brief announcement: the impact of classical electronics constraints on a solid-state logical qubit memory

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ACM Symposium on Parallel Algorithms and Architectures archive
Proceedings of the twenty-first annual symposium on Parallelism in algorithms and architectures table of contents

Calgary, AB, Canada

SESSION: Brief announcements: algorithms meets hardware table of contents

Pages: 166-168

Year of Publication: 2009

ISBN:978-1-60558-606-9

Authors

James E. Levy	Sandia National Laboratories, Albuquerque, NM, USA
Anand Ganti	Sandia National Laboratories, Albuquerque, NM, USA
Cynthia A. Phillips	Sandia National Laboratories, Albuquerque, NM, USA
Benjamin R. Hamlet	Sandia National Laboratories, Albuquerque, NM, USA
Andrew J. Landahl	Sandia National Laboratories, Albuquerque, NM, USA
Thomas M. Gurrieri	Sandia National Laboratories, Albuqueruqe, NM, USA
Robert D. Carr	Sandia National Labortories, Albuquerque, NM, USA
Malcolm S. Carroll	Sandia National Laboratories, Albuquerque, NM, USA

Sponsors

SIGOPS: ACM Special Interest Group on Operating Systems
ACM: Association for Computing Machinery
SIGACT: ACM Special Interest Group on Algorithms and Computation Theory

Publisher

ACM New York, NY, USA

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ABSTRACT

We present and analyze an architecture for a logical qubit memory that is tolerant of faults in the processing of silicon double quantum dot (DQD) qubits. A highlight of our analysis is an in-depth consideration of the constraints faced when integrating DQDs with classical control electronics.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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