Exploring the limits of early register release

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Exploring the limits of early register release: Exploiting compiler analysis

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ACM Transactions on Architecture and Code Optimization (TACO) archive
Volume 6 , Issue 3 (September 2009) table of contents

Article No. 12

Year of Publication: 2009

ISSN:1544-3566

Authors

Timothy M. Jones	University of Edinburgh, Edinburgh, UK
Michael F. P. O'Boyle	University of Edinburgh, Edinburgh, UK
Jaume Abella	Intel Labs Barcelona—UPC
Antonio González	Intel Labs Barcelona—UPC
Oğuz Ergin	TOBB University of Economics and Technology

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ACM New York, NY, USA

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ABSTRACT

Register pressure in modern superscalar processors can be reduced by releasing registers early and by copying their contents to cheap back-up storage. This article quantifies the potential benefits of register occupancy reduction and shows that existing hardware-based schemes typically achieve only a small fraction of this potential. This is because they are unable to accurately determine the last use of a register and must wait until the redefining instruction enters the pipeline. On the other hand, compilers have a global view of the program and, using simple dataflow analysis, can determine the last use. This article evaluates the extent to which compiler analysis can aid early releasing, explores the design space, and introduces commit and issue-based early releasing schemes, quantifying their benefits. Using simple compiler analysis and microarchitecture changes, we achieve 70% of the potential register file occupancy reduction. By adding more hardware support, we can increase this to 94%. Our schemes are compared to state-of-the-art approaches for varying register file sizes and are shown to outperform these existing techniques.

REFERENCES

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