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Tetris-XL: A performance-driven spill reduction technique for embedded VLIW processors

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ACM Transactions on Architecture and Code Optimization (TACO) archive
Volume 6 , Issue 3 (September 2009) table of contents

Article No. 11

Year of Publication: 2009

ISSN:1544-3566

Authors

Weifeng Xu	University of Massachusetts Amherst, Amherst, MA
Russell Tessier	University of Massachusetts Amherst, Amherst, MA

Publisher

ACM New York, NY, USA

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ABSTRACT

As technology has advanced, the application space of Very Long Instruction Word (VLIW) processors has grown to include a variety of embedded platforms. Due to cost and power consumption constraints, many embedded VLIW processors contain limited resources, including registers. As a result, a VLIW compiler that maximizes instruction level parallelism (ILP) without considering register constraints may generate excessive register spills, leading to reduced overall system performance. To address this issue, this article presents a new spill reduction technique that improves VLIW runtime performance by reordering operations prior to register allocation and instruction scheduling. Unlike earlier algorithms, our approach explicitly considers both register reduction and data dependency in performing operation reordering. Data dependency control limits unexpected schedule length increases during subsequent instruction scheduling. Our technique has been evaluated using Trimaran, an academic VLIW compiler, and evaluated using a set of embedded systems benchmarks. Experimental results show that, on average, this technique improves VLIW performance by 10% for VLIW processors with 32 registers and 8 functional units compared with previous spill reduction techniques. Limited improvement is seen versus prior approaches for VLIW processors with 64 registers and 8 functional units.

REFERENCES

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