Quadratic Boolean programming for performance-driven system partitioning

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Quadratic Boolean programming for performance-driven system partitioning

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 761 - 765

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

Minshine Shih
Ernest S. Kuh

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 17, Citation Count: 11

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	E. Balas and J.B. Mazzola, "Quadratic 0-1 Programming by a New Linearization," Presented at the joint ORSA/TIMS National Meeting, Washington, D.C. 1980,
	2	M. Shih, E.$. Kuh and R.-S. Tsay,"Integer Programming Techniques for Mul~way System Partitioning under Timing and Capacity Constraints," Proce~diags, 1993 EuropeanDAC, 1993, pp.294-298
	3	Minshine Shin , Ernest S. Kuh, Quadratic Boolean Programming For Performance-, University of California at Berkeley, Berkeley, CA, 1993
	4	R.E. Burkard and T. Bonniger, "A Heuristic for Quadratic Boole, an Programs with Applications to Quadratic Assignment Problems," European Journal of Operational Research, 1983,13, pp.372-386,
	5	E.R. Barnes, "An Algorithm for Partitioning the Nodes of a Graph," SlAM Journal of Algebraic andDi~crete Methods, 1982, 3(4):541-550,
	6	Earl R. Barnes , Anthony Vannelli , James Q. Walker, A new heuristic for partitioning the nodes of a graph, SIAM Journal on Discrete Mathematics, v.1 n.3, p.299-305, Aug. 1988 [doi>10.1137/0401030]
	7	T. Le~gauex, Combinatorial Algorithms for Integrated Circuit Layout, 1990, Chap 6, pp.285-286,
	8	B.W. Kemighan and S. Lin, "An Efficient Heuristic Procodure for Partitioning Graphs," The Bell System Technical Journal, 49(2). Feb. 1970. pp.291-307
	9	C. M. Fiduccia , R. M. Mattheyses, A linear-time heuristic for improving network partitions, Proceedings of the 19th conference on Design automation, p.175-181, January 1982
	10	Y. W~i and C. Cheng, "Toward Efficient Hierarchical Designs by Ratio Cm Partitioning," Proc. IEEE Int. Conf. on Computer-AidedDesign, 1989, pp.298-301
	11	R.R. Tummala and E.J. Rymaszewski, "Microelectronics Packaging Handbook, Chap. 16," Van Nostrand Reinhold, 1989
	12	S. Mart~llo and P. Toth, "Knapsack Problems," 1990, Chap 7, pp.189-220

CITED BY 11

	Roman Kužnar , Baldomir Zajc , Franc Brglez, A unified cost model for min-cut partitioning with replication applied to optimization of large heterogeneous FPGA partitions, Proceedings of the conference on European design automation, p.271-276, September 19-23, 1994, Grenoble, France
	Lung-Tien Liu , Minshine Shih , Nan-Chi Chou , Chung-Kuan Cheng , Walter Ku, Performance-driven partitioning using retiming and replication, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.296-299, November 07-11, 1993, Santa Clara, California, United States
	Roman Kužnar , Franc Brglez, PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.644-649, November 05-09, 1995, San Jose, California, United States
	Lung-Tien Liu , Ming-Ter Kuo , Shih-Chen Huang , Chung-Kuan Cheng, A gradient method on the initial partition of Fiduccia-Mattheyses algorithm, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.229-234, November 05-09, 1995, San Jose, California, United States
	Dirk Behrens , Klaus Harbich , Erich Barke, Hierarchical partitioning, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.470-477, November 10-14, 1996, San Jose, California, United States
	Lung-Tien Liu , Minshine Shih , Chung-Kuan Cheng, Data flow partitioning for clock period and latency minimization, Proceedings of the 31st annual conference on Design automation, p.658-663, June 06-10, 1994, San Diego, California, United States
	Kai-Yuan Chao , D. F. Wong, Layer assignment for high-performance multi-chip modules, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.680-685, November 06-10, 1994, San Jose, California, United States
	Frank M. Johannes, Partitioning of VLSI circuits and systems, Proceedings of the 33rd annual conference on Design automation, p.83-87, June 03-07, 1996, Las Vegas, Nevada, United States
	Roman Kužnar , Franc Brglez , Baldomir Zajc, Multi-way netlist partitioning into heterogeneous FPGAs and minimization of total device cost and interconnect, Proceedings of the 31st annual conference on Design automation, p.238-243, June 06-10, 1994, San Diego, California, United States
	Shoab A. Khan , Vijay K. Madisetti, System Partitioning of MCMs for Low Power, IEEE Design & Test, v.12 n.1, p.41-52, March 1995
	Gintaras Palubeckis, Iterated Tabu Search for the Unconstrained Binary Quadratic Optimization Problem, Informatica, v.17 n.2, p.279-296, April 2006