Fast approximation of the transient response of Lossy Transmision Line Trees

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Fast approximation of the transient response of Lossy Transmision Line Trees

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 691 - 696

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

M. Sriram
S. M. Kang

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 8, Downloads (12 Months): 15, Citation Count: 8

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	H. B. Bakoglu, Circuits, Interconneclions and Packaging for VLSI, Addison-Wesley, 1990.
	2	J. S. Roychowdhury , A. R. Newton , D. O. Pederson, Simulating lossy interconnect with high frequency nonidealities in linear time, Proceedings of the 29th ACM/IEEE conference on Design automation, p.75-80, June 08-12, 1992, Anaheim, California, United States
	3	Curtis L. Ratzlaff , Nanda Gopal , Lawrence T. Pillage, RICE: Rapid interconnect circuit evaluator, Proceedings of the 28th conference on ACM/IEEE design automation, p.555-560, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127732]
	4	L. Pillage and R. Rohrer, "Asymptotic Waveform Evaluation for Timing Analysis," IEEE Trans. Computer-Aided Design, vol. 9, pp. 352-366, Apr. 1990.
	5	X. Huang, "Padd Approximation of Linear (ized) Circuit Responses," Research Report No. CMU CAD-90-46, Carnegie Mellon University, Dec. 1990.
	6	T. Dhaene and D. De Zutter, "Selection of lumped element models for coupled lossy transmission lines," IEEE Trans. Computer-Aided Design, vol. 11(7), pp. 805-815, July 1992.
	7	D. Zhou, S. Su, F, Tsui, D. S. Gao and J. Cong, "Analysis of Trees of Transmission Lines," UCLA Technical Report CSD-920010, Univ. of California at Los Angeles, 1992.
	8	G. A. Baker, Jr., Essentials of Padd Approximants. Academic Press, 1975.
	9	M. Sriram and S. M. Kang, "Efficient Approximation of the Time Domain Response of Lossy Coupled Transmission Line Trees," Beckman Institute Technical Report UIUC-BI-VLSI-92-03, University of Illinois, Urbana, Dec. 1992.
	10	M. Sriram and S. M. Kang, "Performance Driven MCM Routing Using a Second Order RLC Tree Delay Model," Proc. IEEE Intl. Conf. on Wafer Scale integration, San Francisco, Jan. 1993.
	11	W. C. Elmore, "The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers," J. Applied Phys., 19(1), pp. 55-63, Jan. 1948.

CITED BY 8

	Bernie Sheehan, An AWE technique for fast printed circuit board delays, Proceedings of the 33rd annual conference on Design automation, p.539-543, June 03-07, 1996, Las Vegas, Nevada, United States
	Andrew B. Kahng , Kei Masuko , Sudhakar Muddu, Analytical delay models for VLSI interconnects under ramp input, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.30-36, November 10-14, 1996, San Jose, California, United States
	Zhanhai Qin , Chung-Kuan Cheng, RCLK-VJ network reduction with Hurwitz polynomial approximation, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Xiaodong Yang , Chung Kuan Cheng , Walter H. Ku , Robert J. Carragher, Hurwitz stable reduced order modeling for RLC interconnect trees, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Soroush Abbaspour , Massoud Pedram, Gate delay calculation considering the crosstalk capacitances, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.852-857, January 27-30, 2004, Yokohama, Japan
	Soroush Abbaspour , Massoud Pedram, Calculating the effective capacitance for the RC interconnect in VDSM technologies, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Xiao-Dong Yang , Chung-Kuan Cheng , Walter H. Ku , Robert Carragher, Reduced Order Modeling for RLC Interconnect Tree Using Hurwitz Polynomial, Analog Integrated Circuits and Signal Processing, v.31 n.3, p.193-208, June 2002
	H. H. -F. Jyu , S. Malik, Prediction of interconnect delay in logic synthesis, Proceedings of the 1995 European conference on Design and Test, p.411, March 06-09, 1995