Optimization of combinational logic circuits based on compatible gates

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Optimization of combinational logic circuits based on compatible gates

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 631 - 636

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

Maurizio Damiani
Jerry Chih-Yuan Yang
Giovanni De Micheli

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 11, Citation Count: 3

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	R. Rudell and A. Sangiovanni-Vincentelli, "Multiple-valued minimization for PLA optimization," IEEE Transactions on CAD/ICAS, vol. 6, no. 5, pp. 727-750, Sept. 1987.
	2	Eugene L. Lawler, An Approach to Multilevel Boolean Minimization, Journal of the ACM (JACM), v.11 n.3, p.283-295, July 1964 [doi>10.1145/321229.321232]
	3	R.K. Brayton, R. Rudell, A. Sangiovanni-Vincentelfi, andA. R. Wang, "MIS: A multiple-level logic optimization system," IEEE Transactions on CAD/ICAS, vol. 6, no. 6, pp. 1062-1081, Nov. 1987.
	4	S. Muroga , Y. Kambayashi , H. C. Lai , J. N. Culliney, The Transduction Method-Design of Logic Networks Based on Permissible Functions, IEEE Transactions on Computers, v.38 n.10, p.1404-1424, October 1989 [doi>10.1109/12.35836]
	5	K. A. Bartlett, R. K. Brayton, G. D. Hachtel, R. M. Jacoby, C. R. Morrison, R. L. Rudell, A. Sangiovanni-Vincentelli, and A. R. Wang, "Multilevel logic minimization using implicit don't cares," IEEE Transactions on CAD/ICAS, vol. 7, no. 6, pp. 723-740, June 1988.
	6	R. Brayton and F. Somenzi, "An exact minimizer for boolean relations," in ICCAD, Proceedings of the International Conference on Computer-Aided Design, pp. 316-319, Nov. 1989.
	7	Edward J. McCluskey, Logic design principles with emphasis on testable semicustom circuits, Prentice-Hall, Inc., Upper Saddle River, NJ, 1986
	8	Seh-Woong Jeong , Fabio Somenzi, A new algorithm for the binate covering problem and its application to the minimization of Boolean relations, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.417-420, November 1992, Santa Clara, California, United States
	9	Maurizio Damiani , Jerry C Yang , Giovanni DeMicheli, Optimization of Combinational Logic Circuits Based on Compatible Gates, Stanford University, Stanford, CA, 1993
	10	Randal E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Transactions on Computers, v.35 n.8, p.677-691, Aug. 1986 [doi>10.1109/TC.1986.1676819]
	11	H. Savoj, R. K. Brayton, and H. Touati, "Extracting local don't cares and network optimization," in ICCAD, Proceedings of the International Conference on Computer-Aided Design, pp. 514-517, Nov. 1991.

CITED BY 3

	Shih-Chieh Chang , Lukas P. P. P. van Ginneken , Malgorzata Marek-Sadowska, Fast Boolean optimization by rewiring, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.262-269, November 10-14, 1996, San Jose, California, United States
	Shih-Chieh Chang , Jung-Cheng Chuang , Zhong-Zhen Wu, Synthesis for multiple input wires replacement of a gate for wiring consideration, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.115-119, November 07-11, 1999, San Jose, California, United States
	Shih-Chieh Chang , Malgorzata Marek-Sadowska, Perturb and simplify: multi-level boolean network optimizer, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.2-5, November 06-10, 1994, San Jose, California, United States