A clustering-based optimization algorithm in zero-skew routings

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A clustering-based optimization algorithm in zero-skew routings

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 612 - 616

Year of Publication: 1993

ISBN:0-89791-577-1

Author

Masato Edahiro

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 19, Downloads (12 Months): 77, Citation Count: 41

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 41

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	Masahiko Toyonaga , Keiichi Kurokawa , Takuya Yasui , Atsushi Takahashi, A practical clock tree synthesis for semi-synchronous circuits, Proceedings of the 2000 international symposium on Physical design, p.159-164, May 2000, San Diego, California, United States
	M. Saitoh , M. Azuma , A. Takahashi, Clustering based fast clock scheduling for light clock-tree, Proceedings of the conference on Design, automation and test in Europe, p.240-245, March 2001, Munich, Germany
	Gary Ellis , Lawrence T. Pileggi , Rob A. Rutenbar, A hierarchical decomposition methodology for multistage clock circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.266-273, November 09-13, 1997, San Jose, California, United States
	Jason Cong , Andrew B. Kahng , Cheng-Kok Koh , C.-W. Albert Tsao, Bounded-skew clock and Steiner routing, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.3 n.3, p.341-388, July 1998
	Jatuchai Pangjun , Sachin S. Sapatnekar, Clock distribution using multiple voltages, Proceedings of the 1999 international symposium on Low power electronics and design, p.145-150, August 16-17, 1999, San Diego, California, United States
	Chung-wen Albert Tsao , Cheng-kok Koh, UST/DME: a clock tree router for general skew constraints, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.7 n.3, p.359-379, July 2002
	Zhaoyun Xing , Prithviraj Banerjee, A parallel algorithm for zero skew clock tree routing, Proceedings of the 1998 international symposium on Physical design, p.118-123, April 06-08, 1998, Monterey, California, United States
	Masato Edahiro, An efficient zero-skew routing algorithm, Proceedings of the 31st annual conference on Design automation, p.375-380, June 06-10, 1994, San Diego, California, United States
	Jason Cong , Andrew B. Kahng , Cheng-Kok Koh , C.-W. Albert Tsao, Bounded-skew clock and Steiner routing under Elmore delay, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.66-71, November 05-09, 1995, San Jose, California, United States
	Andrew B. Kahng , C.-W. Albert Tsao, More practical bounded-skew clock routing, Proceedings of the 34th annual conference on Design automation, p.594-599, June 09-13, 1997, Anaheim, California, United States
	Ashok Vittal , Malgorzata Marek-Sadowska, Power optimal buffered clock tree design, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.497-502, June 12-16, 1995, San Francisco, California, United States
	Atsushi Takahashi , Kazunori Inoue , Yoji Kajitani, Clock-tree routing realizing a clock-schedule for semi-synchronous circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.260-265, November 09-13, 1997, San Jose, California, United States
	Joe G. Xi , Wayne W.-M. Dai, Useful-skew clock routing with gate sizing for low power design, Proceedings of the 33rd annual conference on Design automation, p.383-388, June 03-07, 1996, Las Vegas, Nevada, United States
	Yu Chen , Andrew B. Kahng , Gang Qu , Alexander Zelikovsky, The associative-skew clock routing problem, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.168-172, November 07-11, 1999, San Jose, California, United States
	Dennis J. H. Huang , Andrew B. Kahng , Chung-Wen Albert Tsao, On the bounded-skew clock and Steiner routing problems, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.508-513, June 12-16, 1995, San Francisco, California, United States
	Joe G. Xi , Wayne W.-M. Dai, Jitter-tolerant clock routing in two-phase synchronous systems, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.316-320, November 10-14, 1996, San Jose, California, United States
	Andrew B. Kahng , Chung-Wen Albert Tsao, Low-cost single-layer clock trees with exact zero Elmore delay skew, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.213-218, November 06-10, 1994, San Jose, California, United States
	Jatuchai Pangjun , Sachin S. Sapatnekar, Low-power clock distribution using multiple voltages and reduced swings, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.3, p.309-318, June 2002
	Alexander Z. Zelikovsky , Ion I. Măndoiu, Practical approximation algorithms for zero- and bounded-skew trees, Proceedings of the twelfth annual ACM-SIAM symposium on Discrete algorithms, p.407-416, January 07-09, 2001, Washington, D.C., United States
	I-Min Liu , Tan-Li Chou , Adnan Aziz , D. F. Wong, Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion, Proceedings of the 2000 international symposium on Physical design, p.33-38, May 2000, San Diego, California, United States
	Ganesh Venkataraman , C. N. Sze , Jiang Hu, Skew scheduling and clock routing for improved tolerance to process variations, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Andrew B. Kahng , C.-W. Albert Tsao, Practical Bounded-Skew Clock Routing, Journal of VLSI Signal Processing Systems, v.16 n.2-3, p.199-215, June/July 1997
	Massoud Pedram , Hirendu Vaishnav, Power Optimization in VLSI Layout: A Survey, Journal of VLSI Signal Processing Systems, v.15 n.3, p.221-232, March 1997
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	Wai-Ching Douglas Lam , Cheng-Kok Koh, Process variation robust clock tree routing, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Uday Padmanabhan , Janet M. Wang , Jiang Hu, Statistical clock tree routing for robustness to process variations, Proceedings of the 2006 international symposium on Physical design, April 09-12, 2006, San Jose, California, USA
	Monica Donno , Enrico Macii , Luca Mazzoni, Power-aware clock tree planning, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA
	Joe Gufeng Xi , Wayne Wei-Ming Dai, Useful-Skew Clock Routing with Gate Sizing for Low Power Design, Journal of VLSI Signal Processing Systems, v.16 n.2-3, p.163-179, June/July 1997
	Min-Seok Kim , Jiang Hu, Associative skew clock routing for difficult instances, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Ganesh Venkataraman , Jiang Hu , Frank Liu , C-N. Sze, Integrated placement and skew optimization for rotary clocking, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Rupesh S. Shelar, An efficent clustering algorithm for low power clock tree synthesis, Proceedings of the 2007 international symposium on Physical design, March 18-21, 2007, Austin, Texas, USA
	Ganesh Venkataraman , Jiang Hu , Frank Liu, Integrated placement and skew optimization for rotary clocking, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.2, p.149-158, February 2007
	G. Venkataraman , N. Jayakumar , J. Hu , P. Li , Sunil Khatri , Anand Rajaram , P. McGuinness , C. Alpert, Practical techniques to reduce skew and its variations in buffered clock networks, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.592-596, November 06-10, 2005, San Jose, CA
	A. Balboni , C. Costi , A. Pellencin , M. Quadrini , D. Sciuto, Automatic clock tree generation in ASIC designs, Proceedings of the 1995 European conference on Design and Test, p.351, March 06-09, 1995
	Y. P. Chen , D. F. Wong, An Algorithm for Zero-Skew Clock Tree Routing with Buffer Insertion, Proceedings of the 1996 European conference on Design and Test, p.230, March 11-14, 1996
	Hidenori Sato , Akira Onozawa , Hiroaki Matsuda, A Balanced-Mesh Clock Routing Technique Using Circuit Partitioning, Proceedings of the 1996 European conference on Design and Test, p.237, March 11-14, 1996
	Anand Rajaram , David Z. Pan, Robust chip-level clock tree synthesis for SOC designs, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California
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