Performance-driven interconnect design based on distributed RC delay model

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Performance-driven interconnect design based on distributed RC delay model

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 606 - 611

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

Jason Cong
Kwok-Shing Leung
Dian Zhou

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 10, Downloads (12 Months): 53, Citation Count: 46

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	Jason Cong , Lei He, Optimal wiresizing for interconnects with multiple sources, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.4, p.478-511, Oct. 1996
	Jason Cong , Patrick H. Madden, Performance driven global routing for standard cell design, Proceedings of the 1997 international symposium on Physical design, p.73-80, April 14-16, 1997, Napa Valley, California, United States
	Naofumi Tsujii , Katsutoshi Baba , Shuji Tsukiyama, An interconnect topology optimization by a tree transformation, Proceedings of the 2000 conference on Asia South Pacific design automation, p.93-98, January 2000, Yokohama, Japan
	Jason Cong , Lei He, Optimal wiresizing for interconnects with multiple sources, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.568-574, November 05-09, 1995, San Jose, California, United States
	Amir H. Salek , Jinan Lou , Massoud Pedram, A simultaneous routing tree construction and fanout optimization algorithm, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.625-630, November 08-12, 1998, San Jose, California, United States
	Jason Cong , Zhigang Pan , Lei He , Cheng-Kok Koh , Kei-Yong Khoo, Interconnect design for deep submicron ICs, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.478-485, November 09-13, 1997, San Jose, California, United States
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	Sachin S. Sapatnekar, RC interconnect optimization under the Elmore delay model, Proceedings of the 31st annual conference on Design automation, p.387-391, June 06-10, 1994, San Diego, California, United States
	Bharat Krishna , C. Y. Roger Chen , Naresh K. Sehgal, A novel technique for sea of gates global routing, Proceedings of the 10th Great Lakes symposium on VLSI, p.71-74, March 02-04, 2000, Chicago, Illinois, United States
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	John Lillis , Chung-Kuan Cheng , Ting-Ting Y. Lin, Optimal wire sizing and buffer insertion for low power and a generalized delay model, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.138-143, November 05-09, 1995, San Jose, California, United States
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