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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Con90
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J. Cong. Provable good performancedriven global routing. Pvoc. Inte. Conf. on Computer-Aided Design, pages 48-51, 1990.
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DAD+84
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A. E. Dunlop , V. D. Agrawal , D. N. Deutsch , M. F. Jukl , P. Kozak , M. Wiesel, Chip layout optimization using critical path weighting, Proceedings of the 21st conference on Design automation, p.133-136, June 25-27, 1984, Albuquerque, New Mexico, United States
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EM87
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E.Horneber and W. Mathis. A closedform expression for signal delay in cmosdriven branched transmission lines. VLSI, pages 353-362, 1987.
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HNY87
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P.S. Hauge, R. Nair, and E. J. Yoffa. Circuit placement for predictable performance. In IEEE International Conference on Computer-Aided Design,ICCAD- 87, pages 88-91, 1987.
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Hu82
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HXC+92
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X. Hong, T. Xiong, C.K. Cheng, E.S. Kuh, and Jin Huang. Performance-driven steiner tree algorithms for global routing. Research Report, EECS/ERL, UC Berkeley, 1992.
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IC91
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Robert C. Carden, IV , Chung-Kuan Cheng, A global router using an efficient approximate multicommodity multiterminal flow algorithm, Proceedings of the 28th conference on ACM/IEEE design automation, p.316-321, June 17-22, 1991, San Francisco, California, United States
[doi> 10.1145/127601.127687]
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JK89
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JKMS87
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M. A. B. Jackson, E. S. Kuh, and M. Marek-Sadowska. Timing-driven routing for building-block layout. In IEEE International Symposium on Circuits and Systems, pages 518-519, 1987.
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KAE91
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K.Chaudhary, A.Srinivasan, and E.S.Kuh. Ritual: A performance driven placement algorithm for small cell ics. IC- CAD, pages 48-51, 1991.
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ML90
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G. Meixner and U. Lauther. A new global router based on a flow model and linear assignment. ICCAD, 1990.
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MMDN88
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M.Rose, M.Wiesel, D.Kirkpatrick, and N.Nettleton. Dense, performance directed, auto place and route. Proc. CICC, pages 11.1.1-11.1.4, 1988.
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MSL89
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M. Marek-Sadowska and S. P. Lin. Timing-driven placement. IEEE international Conference on Computer-Aided Design ICCAD-89, pages 94-97, 1989.
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Mur83
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K.G. Murty. Linear Programming. John Wiley and Sons, 1983.
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PW90
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S. Prasitjutrakul and W.J.Kubits. A timing-driven global router for custom chip design. Proc. lute. Conf. on Computer-Aided Design, pages 48-51, 1990.
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Sak83
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T. Sakurai. Approximation of wiring delay in mosfet lsi. IEEE J. of Solid-state Circuits, SC-18:418-426, 1983.
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SE90
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TC84
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T.M.Lin and C.A.Mead. Signal delay in general re networks. IEEE Trans. on CAD, CAD-3:331-349, 1984.
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WRBS90
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Wilm E. Donath , Reini J. Norman , Bhuwan K. Agrawal , Stephen E. Bello , Sang Yong Han , Jerome M. Kurtzberg , Paul Lowy , Roger I. McMillan, Timing driven placement using complete path delays, Proceedings of the 27th ACM/IEEE conference on Design automation, p.84-89, June 24-27, 1990, Orlando, Florida, United States
[doi> 10.1145/123186.123232]
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XJCE92
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X.-L. Hong , J. Huang , C.-K. Cheng , E. S. Kuh, FARM: an efficient feed-through pin assignment algorithm, Proceedings of the 29th ACM/IEEE conference on Design automation, p.530-535, June 08-12, 1992, Anaheim, California, United States
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YME90
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Y.Ogawa, M.Pedram, and E.S.Kuh. Timing-driven placement for general cell layout. Proc. Inle. Symp. on circuits and Systems, pages 872-876, 1990.
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YS89
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Y. Fujihara , Y. Sekiyama , Y. Ishibashi , M. Yanaka, DYNAJUST: an efficient automatic routing technique optimizing delay conditions, Proceedings of the 26th ACM/IEEE conference on Design automation, p.791-794, June 25-28, 1989, Las Vegas, Nevada, United States
[doi> 10.1145/74382.74531]
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CITED BY 15
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Feodor F. Dragan , Andrew B. Kahng , Ion Mandoiu , Sudhakar Muddu , Alexander Zelikovsky, Provably good global buffering by multi-terminal multicommodity flow approximation, Proceedings of the 2001 conference on Asia South Pacific design automation, p.120-125, January 2001, Yokohama, Japan
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Feodor F. Dragan , Andrew B. Kahng , Ion Măndoiu , Sudhakar Muddu , Alexander Zelikovsky, Provably good global buffering using an available buffer block plan, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
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Jingyu Xu , Xianlong Hong , Tong Jing , Yici Cai , Jun Gu, A novel timing-driven global routing algorithm considering coupling effects for high performance circuit design, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
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Tong Jing , Xianlong Hong , Haiyun Bao , Yici Cai , Jingyu Xu , Chungkuan Cheng , Jun Gu, UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
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