Synthesis of pipelined instruction set processors

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Synthesis of pipelined instruction set processors

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 583 - 588

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

Richard J. Cloutier
Donald E. Thomas

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 10, Citation Count: 9

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Richard J. Cloutier , Donald E. Thomas, The combination of scheduling, allocation, and mapping in a single algorithm, Proceedings of the 27th ACM/IEEE conference on Design automation, p.71-76, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123230]
	2	P. (3. Paulin mad J. P. Knight, "Force-Directed Scheduling for the Behavioral Synthesis of ASIC's," IEEE Transactions on Computer-Aided Design oflntegrated Circuits, vol. 8, pp. 661-679, June 1989.
	3	N. Park and A. C. Parker, "Schwa: A Software Package for Synthesis of Pipelines from Behavioral Specifications," IEEE Transactions on Computer-Aided Design oflntegrated Circuits, vol. 7, pp. 356-370, Mar 1988.
	4	Cheng-Tsung Hwang , Yu-Chin Hsu , Youn-Long Lin, Scheduling for functional pipelining and loop winding, Proceedings of the 28th conference on ACM/IEEE design automation, p.764-769, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127766]
	5	Peter M. Kogge, The Architecture of Symbolic Computers, McGraw-Hill, Inc., New York, NY, 1990
	6	M. Nourani , C. Papachristou, Move frame scheduling and mixed scheduling-allocation for the automated synthesis of digital systems, Proceedings of the 29th ACM/IEEE conference on Design automation, p.99-105, June 08-12, 1992, Anaheim, California, United States
	7	R. J. Cloutier, Synthesis of Pipelined Instruction Set Processors. l?hl?) thesis, Carnegie Mellon University, httsburgh PA, November 1992.
	8	T. Kiburn, The Manchester University digital computing machine, The early British computer conferences, MIT Press, Cambridge, MA, 1989
	9	IBM, IBM RT PC Hardware Technical Reference Volume 1, first ed., Nov 1985.

CITED BY 9

	Ing-Jer Huang , Alvin M. Despain, Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processors, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.594-599, November 07-11, 1993, Santa Clara, California, United States
	Maria-Cristina V. Marinescu , Martin Rinard, High-level automatic pipelining for sequential circuits, Proceedings of the 14th international symposium on Systems synthesis, September 30-October 03, 2001, Montréal, P.Q., Canada
	Albert E. Casavant, MIST—a design aid for programmable pipelined processors, Proceedings of the 31st annual conference on Design automation, p.532-536, June 06-10, 1994, San Diego, California, United States
	Ing-Jer Huang , Alvin M. Despain, An extended classification of inter-instruction dependency and its application in automatic synthesis of pipelined processors, Proceedings of the 26th annual international symposium on Microarchitecture, p.236-246, December 01-03, 1993, Austin, Texas, United States
	Ing-Jer Huang , Alvin M. Despain, Generating instruction sets and microarchitectures from applications, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.391-396, November 06-10, 1994, San Jose, California, United States
	Forrest Brewer , Steve Haynal, Symbolic NFA scheduling of a RISC microprocessor, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.4, p.429-434, August 2002
	Fei Sun , Srivaths Ravi , Anand Raghunathan , Niraj K. Jha, Synthesis of custom processors based on extensible platforms, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.641-648, November 10-14, 2002, San Jose, California
	Sofiéne Tahar , Ramayya Kumar, A Practical Methodology for the Formal Verification of RISC Processors, Formal Methods in System Design, v.13 n.2, p.159-225, Sept. 1998
	A. E. Casavant, Balancing structural hazards and hardware cost of pipelined processors, Proceedings of the 1995 European conference on Design and Test, p.562, March 06-09, 1995