Critical path minimization using retiming and algebraic speed-up

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Critical path minimization using retiming and algebraic speed-up

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 573 - 577

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

Zia Iqbal
Miodrag Potkonjak
Sujit Dey
Alice Parker

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 14, Downloads (12 Months): 60, Citation Count: 10

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	Bre74	Richard P. Brent, The Parallel Evaluation of General Arithmetic Expressions, Journal of the ACM (JACM), v.21 n.2, p.201-206, April 1974 [doi>10.1145/321812.321815]
	Bra90	R. Brayton, et al.,"Multilevel Logic Synthesis", Proc. of the IEEE", pp. 264-300, Vol. 78, No. 2, Feb. 1990.
	Cha92	Anantha P. Chandrakasan , Miodrag Potkonjak , Jan Rabaey , Robert W. Brodersen, HYPER-LP: a system for power minimization using architectural transformations, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.300-303, November 1992, Santa Clara, California, United States
	DeM91	G. De Micheli: "Synchronous Logic Synthesis: Algorithms for Cycle-Time Minimization", IEEE Trans. on CAD, Vol. 10, No. 1, pp. 63-73, 1991.
	Dey92	Sujit Dey , Miodrag Potkonjak , Steven G. Rothweiler, Performance optimization of sequential circuits by eliminating retiming bottlenecks, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.504-509, November 1992, Santa Clara, California, United States
	Fis85	Charles N. Fischer , Richard J. LeBlanc, Jr., Crafting a compiler, Benjamin-Cummings Publishing Co., Inc., Redwood City, CA, 1988
	Goo90	G. Goossens, et. al. : "An Efficient Microcode Compiler for Application Specific DSP Processors", IEEE Trans. on CAD, Vol. 9, No. 9, pp. 925-937, 1990.
	Gyr84	E. Gyrczyc: "Automatic Generation of Microsequenced Data Paths to Realize ADA Circuit Description", Ph. D. Thesis, Carleton University, 1984.
	Har89a	R. Hartley, A. Casavant: "Tree-height Minimization in Pipelined Architectures", 1EEE IC CAD, pp.l12-115, 1989.
	Har89b	B.S. Haroun, M.I. Elmasry: "Architectural Synthesis for DSP Silicon Compilers", IEEE Transaction on CAD for IC, Vol. 8, No. 4, pp. 431-447, 1989.
	Iqb93	Z. Iqbal, M. Potkonjak, S. Dey, A. Parker: "Critical Path Minimization Using Retiming and Algebraic Speed- Up", Technical Report #93-C003-4-5510-1, NEC USA, 1993.
	Lei91	C.E. Leiserson, J.B. Saxe: "Retiming Synchronous Circuitry", Algorithmica, Vol. 6, pp. 5-35, 1991
	Mal91	S. Malik, et al.: "Retiming and Resynthesis: Optimizing Sequential Networks with Combinatorial Techniques", IEEE Trans. on CAD, Vol. 10, No. 1, pp. 74-84, 1991.
	McF83	M.C. McFarland, A.C. Parker: "An Abstract Model of Behavior for Hardware Descriptions", IEEE Transaction on Computers, Vol. 32, No. 7, pp. 621-636, 1983.
	Par88	N. Park, A.C. Parker: "Sehwa: A Software Package for Synthesis of Pipelines from Behavioral Specifications", IEEE Trans. on CAD, Vol 7, No. 3, pp. 356-370, 1988.
	Pau89	P.G. Paulin, J.P. Knight: "Force -Directed Scheduling for the Behavioral Synthesis of ASIC", IEEE Trans. on CAD, Vol 8., No 6, pp. 661-679, 1989.
	Pot90	M. Potkonjak and J. Rabaey, "Retiming for Scheduling", VLSI Signal Processing, pp. 23-32, San Diego, Nov. 1990.
	Pot92	Miodrag Potkonjak , Jan Rabaey, Maximally fast and arbitrarily fast implementation of linear computations, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.304-308, November 1992, Santa Clara, California, United States
	Rab91	J. M. Rabaey , C. Chu , P. Hoang , M. Potkonjak, Fast Prototyping of Datapath-Intensive Architectures, IEEE Design & Test, v.8 n.2, p.40-51, April 1991 [doi>10.1109/54.82037]
	Sin88	K. J. Singh, et. al.: "Timing Optimization of Combinational Logic", IEEE ICCAD, pp. 282-285, 1988.
	Tri87	H_ Tricker: "Flamel: A hil~h-kevel Hardware Compiler". IEEE Trans. on CAD, Vol. 6, No. 2, pp. 259-269, 1987.
	Wal89	R.A. Walker, D.E. Thomas: "Behavioral Transformation for Algorithmic Level IC Design", IEEE Trans. on CAD, Vol 8. No.10, pp. 1115-1127, 1989.

CITED BY 10

	Michael Sheliga , Edwin Hsing Mean Sha, Global node reduction of linear systems using ratio analysis, Proceedings of the 7th international symposium on High-level synthesis, p.140-145, May 18-20, 1994, Niagra-on-the-Lake, Ontario, Canada
	Inki Hong , Miodrag Potkonjak , Ramesh Karri, Power optimization using divide-and-conquer techniques for minimization of the number of operations, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.4 n.4, p.405-429, Oct. 1999
	Peter F. A. Middelhoek , Sreeranga P. Rajan, From VHDL to efficient and first-time-right designs: a formal approach, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.2, p.205-250, April 1996
	Birger Landwehr , Peter Marwedel, A new optimization technique for improving resource exploitation and critical path minization, Proceedings of the 10th international symposium on System synthesis, p.65-72, September 17-19, 1997, Antwerp, Belgium
	Surendra Bommu , Niall O'Neill , Maciej Ciesielski, Retiming-based factorization for sequential logic optimization, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.3, p.373-398, July 2000
	Sumit Gupta , Mehrdad Reshadi , Nick Savoiu , Nikil Dutt , Rajesh Gupta , Alex Nicolau, Dynamic common sub-expression elimination during scheduling in high-level synthesis, Proceedings of the 15th international symposium on System Synthesis, October 02-04, 2002, Kyoto, Japan
	David J. Kolson , Alexandru Nicolau , Nikil Dutt, Integrating program transformations in the memory-based synthesis of image and video algorithms, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.27-30, November 06-10, 1994, San Jose, California, United States
	Wei-Kai Cheng , Youn-Long Lin, A transformation-based approach for storage optimization, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.158-163, June 12-16, 1995, San Francisco, California, United States
	Sumit Gupta , Rajesh Kumar Gupta , Nikil D. Dutt , Alexandru Nicolau, Coordinated parallelizing compiler optimizations and high-level synthesis, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.9 n.4, p.441-470, October 2004
	N. Julien , S. Gailhard , E. Martin, Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT, Journal of VLSI Signal Processing Systems, v.35 n.2, p.195-211, September 2003