A bounded 2D contour searching algorithm for floorplan design with arbitrarily shaped rectilinear and soft modules

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A bounded 2D contour searching algorithm for floorplan design with arbitrarily shaped rectilinear and soft modules

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 525 - 530

Year of Publication: 1993

ISBN:0-89791-577-1

Author

Tsu-chang Lee

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 9, Downloads (12 Months): 21, Citation Count: 9

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Lu She, A Macro Cell Placement Algorithm Using Mathematical Programming Techniques, Ph.D dissertation, Stanford University, March 1989.
	2	Ting-chi Wang , D. F. Wong, An optimal algorithm for floorplan area optimization, Proceedings of the 27th ACM/IEEE conference on Design automation, p.180-186, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123253]
	3	H. Onodera, Y. Taniguchi, and K. Tamaru, "Branch-and-Bound Placement for Building Block Layout", presented at, 1990 international Workshop on Layout Synthesis, 1990. "
	4	Albert H. Chao, Eric M. Nequist, Thanh D. Vuong, "Direct Solution of Performance Constraints During Placement", in IEEE 1990 Custom Integrated Circuits Conference, pp.27.2.1-27.2.4.
	5	S. Kirkpatrick, C. Gelatt, and M. Vecchi, "Optimization by Simulated Annealing", Science, voi.220, n.4598, May 13, 1983, pp.671.
	6	Carl Sechen, Placement and Global Routing of Integrated Circuits Using Simulated Annealing, Ph.D dissertation, Univ. of California, Berkeley, 1987.
	7	Hyunchul Shin , Alberto L. Sangiovanni-Vincentelli , Carlo H. Séquin, Two-dimensional compaction by “zone refining”, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.115-122, July 1986, Las Vegas, Nevada, United States
	8	W.H. Wolf, R.G. Mathews, :I.A. Mewkirk, and R.W. Dutton, "Algorithms for Optimizing Two-Dimensional Symbolic Layout Compaction", IEEE Trans. CAD of IC and Systems, CAD-7(4), 1988, pp.451-466.
	9	Ping-San Tzeng , Carlo H. Séquin, Macro-block placement using efficient 2-D compaction, Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI, p.178-191, April 1991
	10	W.W.-M. Dai and E.S. Kuh, "Simultaneous Floorplanning and Global Routing for Hierarchical Building Block Layout", IEEE Trans on Computer.Aided Design of Integrated Circuits and Systems, CAD-6(5),1987, pp.828-837.
	11	G. Vijayan and R.S. Tsay, "Floorplanning by Topological Constraint Reduction" 1990 IEEE International Conference on Computer-Aided Design, pp.106-109.
	12	Tsu-chang Lee, "Multiple-Layer Contour Searching Method and Apparatus for Circuit Building Block Placement", US patent pending.

CITED BY 9

	Andrew B. Kahng, Classical floorplanning harmful?, Proceedings of the 2000 international symposium on Physical design, p.207-213, May 2000, San Diego, California, United States
	Maggie Zhiwei Kang , Wayne Wei-Mingi Dai, Arbitrary rectilinear block packing based on sequence pair, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.259-266, November 08-12, 1998, San Jose, California, United States
	Shigetoshi Nakatake , Kunihiro Fujiyoshi , Hiroshi Murata , Yoji Kajitani, Module placement on BSG-structure and IC layout applications, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.484-491, November 10-14, 1996, San Jose, California, United States
	Yun-Chih Chang , Yao-Wen Chang , Guang-Ming Wu , Shu-Wei Wu, B*-Trees: a new representation for non-slicing floorplans, Proceedings of the 37th conference on Design automation, p.458-463, June 05-09, 2000, Los Angeles, California, United States
	Jin Xu , Pei-Ning Guo , Chung-Kuan Cheng, Cluster refinement for block placement, Proceedings of the 34th annual conference on Design automation, p.762-765, June 09-13, 1997, Anaheim, California, United States
	Swanwa Liao , Mario A. Lopez , Dinesh Mehta, Constrained polygon transformations for incremental floorplanning, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.3, p.322-342, July 2001
	Jin Xu , Pei-ning Guo , Chung-Kuan Cheng, Rectilinear block placement using sequence-pair, Proceedings of the 1998 international symposium on Physical design, p.173-178, April 06-08, 1998, Monterey, California, United States
	Dinesh P. Mehta , Naveed Sherwani, On the use of flexible, rectilinear blocks to obtain minimum-area floorplans in mixed block and cell designs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.1, p.82-97, Jan. 2000
	Guang-Ming Wu , Yun-Chih Chang , Yao-Wen Chang, Rectilinear block placement using B*-trees, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.8 n.2, p.188-202, April 2003