An algorithm for diagnosing two-line bridging faults in combinational circuits

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An algorithm for diagnosing two-line bridging faults in combinational circuits

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 520 - 524

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

Sreejit Chakravarty
Yiming Gong

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 8, Downloads (12 Months): 18, Citation Count: 4

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	M. Abramovici and M. Breuer, "A Practical Approach to Fault Simulation and Test Generation for Bridging Faults", IEEE Trans. on Comp., Vol. C-34, No. 7, pp. 658- 663.
	2	F. Brglez and H. Fujiwara, "A Neutral Netlist of l0 Combinational Benchmark Circuits and a Target Translator in Fortran", special session on ATPG and Fault simulation, IEEE Int'l. Symposium on Circuits and Systems, 1985.
	3	D. J. Burns, "Locating High Resistance Shorts in " CMOS Circuits by Analyzing Supply Current Measurement Vectors", Int'l Symposium for Testing and Failure Analysis, pp. 231- 237, 1989.
	4	Sreejit Chakravarty , Minsheng Liu, Algorithms for IDDQ measurement based diagnosis of bridging faults, Journal of Electronic Testing: Theory and Applications, v.3 n.4, p.377-385, Dec. 1992 [doi>10.1007/BF00135341]
	5	S. Chakravarty, Y. Gong, "An Algorithm for Diagnosing Two-Line Bridging Faults in Combinational Circuits", Tech. Rep. No. 92-26, Dept. of Comp. Science, SUNY at Buffalo, Buffalo, NY 14260.
	6	F.T.Ferguson and J.P.Shen, "A CMOS Fault Extractor for Inductive Fault Analysis", IEEE Trans. on Comput.-Aided Design, Vol. 7, No. 11, pp. 1181-1194.
	7	T. Larabee, "Test Pattern Generation Using Boolean Satisfiability", IEEE Transaction on Comput.-Aided Design, Vol. 11, No. 1, pp. 4-15.
	8	F. Maamari and J. Rajski, "A Method of Fault Simulation Based on Stem Regions", IEEE Trans. on CAD, Vol. CAD-9, No. 2, pp. 212-.
	9	S. D. Millman, Edward J. McCluskey and J. M. Acken, "Diagnosing CMOS Bridging Faults with Stuck-at Fault Dictionaries", 1990 ITC, pp. 860-870.

CITED BY 4

	Srikanth Venkataraman , W. Kent Fuchs, A deductive technique for diagnosis of bridging faults, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.562-567, November 09-13, 1997, San Jose, California, United States
	Brian Chess , David B. Lavo , F. Joel Ferguson , Tracy Larrabee, Diagnosis of realistic bridging faults with single stuck-at information, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.185-192, November 05-09, 1995, San Jose, California, United States
	Yiming Gong , Sreejit Chakravarty, On adaptive diagnostic test generation, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.181-184, November 05-09, 1995, San Jose, California, United States
	Irith Pomeranz , Sudhakar M. Reddy, Location of Stuck-At Faults and Bridging Faults Based on Circuit Partitioning, IEEE Transactions on Computers, v.47 n.10, p.1124-1135, October 1998