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TIM: a timing package for two-phase, level-clocked circuitry

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 497 - 502

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

Marios C. Papaefthymiou
Keith H. Randall

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 8, Downloads (12 Months): 11, Citation Count: 9

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	2	T. Burks, K. Sakallah, and T. Mudge. Multiphase retiming using minTc. T92 A CM Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, March 1992.
	3	James J. Cherry, Pearl: a CMOS timing analyzer, Proceedings of the 25th ACM/IEEE conference on Design automation, p.148-153, June 12-15, 1988, Atlantic City, New Jersey, United States
	4	Thomas T. Cormen , Charles E. Leiserson , Ronald L. Rivest, Introduction to algorithms, MIT Press, Cambridge, MA, 1990
	5	Michael R. Dagenais , Nicholas C. Rumin, Automatic determination of optimal clocking parameters in synchronous MOS VLSI circuits, Proceedings of the fifth MIT conference on Advanced research in VLSI, p.19-33, January 1988, Cambridge, Massachusetts, United States
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	7	Alexander T. Ishii , Charles E. Leiserson, A timing analysis of level-clocked circuitry, Proceedings of the sixth MIT conference on Advanced research in VLSI, p.113-130, March 1990, Boston, Massachusetts, United States
	8	A. T. Ishii, C. E. Leiserson, and M. C. Papaefthymiou. Optimizing two-phase, level-clocked circuitry. In Advanced Research in VLSI and Parallel Systems: Proc. of the 1992 Brown/MIT Conference. MIT Press, March 1992.
	9	Norman P. Jouppi, Timing analysis for nMOS VLSI, Proceedings of the 20th conference on Design automation, p.411-418, June 27-29, 1983, Miami Beach, Florida, United States
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	16	J.K. Ousterhout. Switch-level timing verifier for digital MOS VLSI. IEEE Trans. Computer-Aided Design, CAD-4:336-349, July 1985.
	17	M. C. Papaefthymiou. Sensitivity analysis of synchronous circuitry. Unpublished manuscript, August 1992.
	18	M. C. Papaefthymiou and K. H. Randall. TIM: an interactive timing optimization tool for level-clocked circuits. July 1992. User's Guide and Reference Manual, under preparation.
	19	Marios C. Papaefthymiou , Keith H. Randall, Edge-triggering vs. two-phase level-clocking, Proceeding of the 1993 symposium on Research on integrated systems, p.201-218, February 1993, Seattle, Washington, United States
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CITED BY 9

	Xun Liu , Marios C. Papaefthymiou , Eby G. Friedman, Maximizing performance by retiming and clock skew scheduling, Proceedings of the 36th ACM/IEEE conference on Design automation, p.231-236, June 21-25, 1999, New Orleans, Louisiana, United States
	Naresh Maheshwari , Sachin S. Sapatnekar, Minimum area retiming with equivalent initial states, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.216-219, November 09-13, 1997, San Jose, California, United States
	N. Maheshwari , S. S. Sapatnekar, Efficient minarea retiming of large level-clocked circuits, Proceedings of the conference on Design, automation and test in Europe, p.840-847, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Kumar N. Lalgudi , Marios C. Papaefthymiou, DELAY: an efficient tool for retiming with realistic delay modeling, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.304-309, June 12-16, 1995, San Francisco, California, United States
	Marios C. Papaefthymiou, Asymptotically efficient retiming under setup and hold constraints, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.396-401, November 08-12, 1998, San Jose, California, United States
	Alexander T. Ishii , Charles E. Leiserson , Marios C. Papaefthymiou, Optimizing two-phase, level-clocked circuitry, Journal of the ACM (JACM), v.44 n.1, p.148-199, Jan. 1997
	Narendra Shenoy , Richard Rudell, Efficient implementation of retiming, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.226-233, November 06-10, 1994, San Jose, California, United States
	Xun Liu , Marios C. Papaefthymiou , Eby G. Friedman, Minimizing sensitivity to delay variations in high-performance synchronous circuits, Proceedings of the conference on Design, automation and test in Europe, p.126-es, January 1999, Munich, Germany
	Hai Zhou, A new efficient retiming algorithm derived by formal manipulation, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.1, p.1-19, January 2008