Sequential circuit delay optimization using global path delays

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Sequential circuit delay optimization using global path delays

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 483 - 489

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

Srimat T. Chakradhar
Sujit Dey
Miodrag Potkonjak
Steven G. Rothweiler

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 10, Downloads (12 Months): 19, Citation Count: 7

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	C. E. Leiserson and J. B. Saxe, "Retiming Synchronous Circuitry," AIgorithmica, vol. 6, pp. 5-35, 1991.
	2	G. D. Micheli, "Synchronous Logic Synthesis: Algorithms for Cycle-Time Minimization," IEEE Transactions on Computer-Aided Design, vol. 10, pp. 63-73, January 1991.
	3	S. Malik, E. Sentovich, R. Brayton, and A. Sangiovarmi- Vincentelli, "Retiming and Resynthesis: Optimizing Sequential Networks with Combinational Techniques," IEEE Transactzons on Computer-Aided Design, vol. 10, pp. 74- 84, January 1991.
	4	Sujit Dey , Miodrag Potkonjak , Steven G. Rothweiler, Performance optimization of sequential circuits by eliminating retiming bottlenecks, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.504-509, November 1992, Santa Clara, California, United States
	5	S.T. Chakradhar, S. Dey, M. Potkonjak, and S. Rothweiler, "Sequential Circuit Delay Optimization Using Global Path Delays," Tech. Rep. 93-C006-4-5506-3, NEC USA, Princeton, N J, 1993.
	6	Christos H. Papadimitriou , Kenneth Steiglitz, Combinatorial optimization: algorithms and complexity, Prentice-Hall, Inc., Upper Saddle River, NJ, 1982
	7	Ellen Sentovich , Kanwar Jit Singh , Cho W. Moon , Hamid Savoj , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Sequential Circuit Design Using Synthesis and Optimization, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.328-333, October 11-14, 1992
	8	CPLEX. CPLEX Optimization, Inc., 930 Tahoe Blvd., Bldg. 802, Incline Village, NV 89451-9436, 1992.

CITED BY 7

	Soha Hassoun , Carl Ebeling, Architectural retiming: pipelining latency-constrained circuits, Proceedings of the 33rd annual conference on Design automation, p.708-713, June 03-07, 1996, Las Vegas, Nevada, United States
	Balakrishnan Iyer , Maciej Ciesielski, Reencoding for cycle-time minimization under fixed encoding length, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.312-315, November 08-12, 1998, San Jose, California, United States
	Peichen Pan, Performance-driven integration of retiming and resynthesis, Proceedings of the 36th ACM/IEEE conference on Design automation, p.243-246, June 21-25, 1999, New Orleans, Louisiana, United States
	Surendra Bommu , Niall O'Neill , Maciej Ciesielski, Retiming-based factorization for sequential logic optimization, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.3, p.373-398, July 2000
	Soha Hassoun , Tiziano Villa, Optimization of synchronous circuits, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Jason Cong , Chang Wu, FPGA synthesis with retiming and pipelining for clock period minimization of sequential circuits, Proceedings of the 34th annual conference on Design automation, p.644-649, June 09-13, 1997, Anaheim, California, United States
	Karam S. Chatha , Ranga Vemuri, Hardware-Software partitioning and pipelined scheduling of transformative applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.3, p.193-208, June 2002