Minimum length synchronizing sequences of finite state machine

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Minimum length synchronizing sequences of finite state machine

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 463 - 468

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

June-Kyung Rho
Fabio Somenzi
Carl Pixley

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 7, Downloads (12 Months): 12, Citation Count: 4

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	CJSP93	H. Cho, S.-W. Jeong, F Somenzl, and C. Pixley. Synchronizing sequences and symbolic traversal techniques in test generation. Journal of Electronw Testzng: Theory and Apl~cat~ons, 1993 To appear.
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	PJH92	C. Pixley , S.-W. Jeong , G. D. Hachtel, Exact calculation of synchronization sequences based on binary decision diagrams, Proceedings of the 29th ACM/IEEE conference on Design automation, p.620-623, June 08-12, 1992, Anaheim, California, United States
	RS92	J.-K. Rho , F. Somenzi, Inductive verification of iterative systems, Proceedings of the 29th ACM/IEEE conference on Design automation, p.628-633, June 08-12, 1992, Anaheim, California, United States
	SSM+92	Ellen Sentovich , Kanwar Jit Singh , Cho W. Moon , Hamid Savoj , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Sequential Circuit Design Using Synthesis and Optimization, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.328-333, October 11-14, 1992
	TSL+90	H. Touati, H Savoj, B. Lin, R. K. Brayton, and A. Sangiovanni-V1ncentelli. Implicit enumeration of finite state machines using BDD's. In Proceedzngs of the IEEE International Conference on Computer A~ded Design, pages 130-133, November 1990.
	Yan91	S. Yang. Logic synthesis and optimization benchmarks user guide version 3.0. Technical report, Microelectronlcs Center of North Carolina, :Research Triangle Park, NC, January 1991.

CITED BY 4

	Kwang-Ting Cheng, Gate-level test generation for sequential circuits, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.4, p.405-442, Oct. 1996
	F. Corno , P. Prinetto , M. Rebaudengo , M. Sonza Reorda , G. Squillero, Initializability analysis of synchronous sequential circuits, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.7 n.2, p.249-264, April 2002
	Jalal A. Wehbeh , Daniel G. Saab, Initialization of Sequential Circuits and its Application to ATPG, Journal of Electronic Testing: Theory and Applications, v.13 n.3, p.259-271, Dec. 1998
	Piergiorgio Bertoli , Alessandro Cimatti , Marco Roveri, Heuristic search + symbolic model checking = efficient conformant planning, Proceedings of the 17th international joint conference on Artificial intelligence, p.467-472, August 04-10, 2001, Seattle, WA, USA