Bridge fault simulation strategies for CMOS integrated circuits

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Bridge fault simulation strategies for CMOS integrated circuits

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 458 - 462

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

Brian Chess
Tracy Larrabee

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 12, Downloads (12 Months): 26, Citation Count: 9

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	M. Abramovici and P. R. Menon. A practical approach to fault simulation and test generation for bridging faults. IEEE Transactions on Computers, C-34:658-663, 1985.
	2	John M. Acken, Testing for bridging faults (shorts) in CMOS circuits, Proceedings of the 20th conference on Design automation, p.717-718, June 27-29, 1983, Miami Beach, Florida, United States
	3	J. M. Acken. Deriving Accurate Fault Models. PhD thesis, Stanford University, Department of Electrical Engineering, September 1988.
	4	J. M. Acken and S. D. Millman. Accurate modeling and simulation of bridging faults. In Proceedings o,f the Custom Integrated Circuits Conference, pages 17.4.1-17.4.4, 1991.
	5	J. M. Acken and S. D. Millman. Fault model evolution for diagnosis: Accuracy vs precision. In Proceedings o} the Custom Integrated Circuits Con}erence, 1992.
	6	F. Brglez and H. Fujiwara. A neutral netlist of 10 'combinatorial benchmark circuits and a target translator in fortran. In Inter**ational Symposium on Circuits and Systems. IEEE, June 1985.
	7	F. Joel Ferguson , Tracy Larrabee, Test Pattern Generation for Realistic Bridge Faults in CMOS ICs, Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner, p.492-499, October 26-30, 1991
	8	F. J. Ferguson and J. P. Shen. A CMOS fault extractor for inductive fault analysis. IEEE Transactions on Computer- Aided Design, 7(11):1181-1194, November 1988.
	9	A. Friedman. Diagnosis of short-circuit faults in combinational circuits. IEEE Transactions on Computers, pages 750- 752, July 1974.
	10	Alvin Jee and F. Joel Ferguson. Carafe: An inductive fault analysis tool for cmos vlsi circuits. In Proceedings o} the IEEE VLSI Test Symposium, page in press, 1993.
	11	T. Larrabee. Test pattern generation using boolean satisfiability. IEEE Transactions on Computer.Aided Design, pages 6-22, January 1992.
	12	K.C.Y. Mei. Bridging and stuck-at faults. IEEE Transactions on Computers, C-23(7):720-727, July 1974_
	13	J.P. Shen, W. Maly, and F.J. Ferguson. Inductive fault analysis of MOS integrated circuits. IEEE Design and Test of Computers, 2(6):13-26, December 1985.
	14	J.A. Waicukauski, E. B. Eichelberger, D. O. Forlenza, E. Lindbloom, and T. McCarthy. Fault simulation for structured VLSI. VLSI Design, VI:20-32, 1985.

CITED BY 9

	Brian Chess , David B. Lavo , F. Joel Ferguson , Tracy Larrabee, Diagnosis of realistic bridging faults with single stuck-at information, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.185-192, November 05-09, 1995, San Jose, California, United States
	Tzuhao Chen , Ibrahim N. Hajj, GOLDENGATE: a fast and accurate bridging fault simulator under a hybrid logic/IDDQ testing environment, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.555-561, November 09-13, 1997, San Jose, California, United States
	Amir Attarha , Mehradad Nourani , Carco Lucas, Modeling and simulation of real defects using fuzzy logic, Proceedings of the 37th conference on Design automation, p.631-636, June 05-09, 2000, Los Angeles, California, United States
	Charles E. Stroud , James R. Bailey , Johan R. Emmert, A New Method for Testing Re-Programmable PLAs, Journal of Electronic Testing: Theory and Applications, v.16 n.6, p.635-640, Dec. 2000
	Kuen-Jong Lee , Jing-Jou Tang , Tsung-Chu Huang, BIFEST: a built-in intermediate fault effect sensing and test generation system for CMOS bridging faults, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.4 n.2, p.194-218, April 1999
	R. D. (Shawn) Blanton , John P. Hayes, On the properties of the input pattern fault model, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.8 n.1, p.108-124, January 2003
	Brian Chess , Tracy Larrabee, Logic Testing of Bridging Faults in CMOS Integrated Circuits, IEEE Transactions on Computers, v.47 n.3, p.338-345, March 1998
	Khurram Muhammad , Kaushik Roy, Fault Detection and Location Using IDD Waveform Analysis, IEEE Design & Test, v.18 n.1, p.42-49, January 2001
	M. B. Santos , J. P. Teixeira, Defect-oriented mixed-level fault simulation of digital systems-on-a-chip using HDL, Proceedings of the conference on Design, automation and test in Europe, p.111-es, January 1999, Munich, Germany