Design for testability for path delay faults in sequential circuits

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Design for testability for path delay faults in sequential circuits

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 453 - 457

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

Tapan J. Chakraborty
Vishwani D. Agrawal
Michael L. Bushnell

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 8, Downloads (12 Months): 16, Citation Count: 5

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	S. Devadas, "Delay Test Generation for Synchronous Sequential Circuits," Proc. int. Test Conf., pp. 144-152, 1989.
	2	P. Agrawal, V.D. Agrawal, and S.C. Seth, "A New Method for Generating Tests for Delay Faults in Non-Scan Circuits," Proc. 5th Intl. Conf. VLSI Design, pp. 4-11, January 1992.
	3	T. J. Chakraborty , V. D. Agrawal , M. L. Bushnell, Delay fault models and test generation for random logic sequential circuits, Proceedings of the 29th ACM/IEEE conference on Design automation, p.165-172, June 08-12, 1992, Anaheim, California, United States
	4	T.J. Chakraborty, V.D. Agrawal, and M.L. Bushnell, "Path Delay Fault Simulation Algorithms for Sequential Circuits," Proc. Asian Test Syrup., pp. 52-56, November 1992.
	5	Kwang-Ting Cheng, Test generation for delay faults in non-scan and partial scan sequential circuits, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.554-559, November 1992, Santa Clara, California, United States
	6	Y.K. Malaiya and R. Narayanaswamy, "Modeling and Testing for Timing Faults in Synchronous Sequential circuits," IEEE Design & Test of Computers, Vol. 1, pp. 62-74, November 1984.
	7	S. DasGupta, P. Goel, R.G. Walther, and T.W. Williams, "A Variation of LSSD and its Implications on Design and Test Pattern Generation in VLSI," Int. Test Conf. Digest of Papers, Philadelphia, PA, pp. 63-66, November 1982.
	8	A.K. Prarnanick and S.M. Reddy, "On the Design of Path Delay Fault Testable Combinational Circuits," Fault Tolerant Comput. Syrup. (FTCS-20) Digest of Papers, pp. 374-381, June 1990.
	9	C.J. Lin and S.M. Reddy, "On Delay Fault Testing in Logic Circuits," IEEE Trans. CAD, Vol. 6, pp. 694-701, September 1987.
	10	B. Bencivenga, T.J. Chakraborty, and S. Davidson, "The Architecture of the GenTest Sequential Circuit Test Generatot," Proc. Cust. integr. Circ. Conf., pp. 17.1.1-17.1.4, May 1991.
	11	K.-T. Cheng , V. D. Agrawal, A Partial Scan Method for Sequential Circuits with Feedback, IEEE Transactions on Computers, v.39 n.4, p.544-548, April 1990 [doi>10.1109/12.54847]
	12	S. Bhawmik, C.J. Lin, K.-T. Cheng, and V.D. Agrawal, "PASCANT: A Partial Scan and Test Generation System," Proc. Cast. lntegr. Circ. Conf., pp. 17.3.1-17.3.4, May 1991.

CITED BY 5

	Clay Gloster , Franc Brglez, Partial scan selection for user-specified fault coverage, Proceedings of the conference on European design automation, p.111-116, September 18-22, 1995, Brighton, England
	Wen-Chang Fang , Sandeep K. Gupta, Clock grouping: a low cost DFT methodology for delay testing, Proceedings of the 31st annual conference on Design automation, p.94-99, June 06-10, 1994, San Diego, California, United States
	Kwang-Ting Cheng , Angela Krstic , Hsi-Chuan Chen, Generation of High Quality Tests for Robustly Untestable Path Delay Faults, IEEE Transactions on Computers, v.45 n.12, p.1379-1392, December 1996
	D. Maruyama , A. Kanuma , T. Mochiyama , H. Komatsu , Y. Sugiyama , N. Ito, Detection of multiple transitions in delay fault test of SPARC64 microprocessor, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.893-898, November 07-11, 2004
	Vlado Vorisek , Thomas Koch , Hermann Fischer, At-Speed Testing of SOC ICs, Proceedings of the conference on Design, automation and test in Europe, p.30120, February 16-20, 2004