Delay fault coverage and performance tradeoffs

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Delay fault coverage and performance tradeoffs

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 446 - 452

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

William K. Lam
Alexander Saldanha
Robert K. Brayton
Alberto L. Sangiovanni-Vincentelli

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 12, Downloads (12 Months): 21, Citation Count: 19

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Srinivas Devadas , Kurl Keutzer, Necessary and sufficient conditions for robust delay-fault testability of combinational logic circuits, Proceedings of the sixth MIT conference on Advanced research in VLSI, p.221-238, March 1990, Boston, Massachusetts, United States
	2	William K. Lam , Alexander Saldanha , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Delay fault testing: trading fault coverage, test set size, and performance, Proceeding of the 1993 symposium on Research on integrated systems, p.68-87, February 1993, Seattle, Washington, United States
	3	Y. Malaiya and R. Narayanswamy. Testing for timing faults in synchronous sequential integrated circuits. In Proceedings of the International Test Conference, pages 560--571, October 1983.
	4	Patrick C. McGeer , Robert K. Brayton, Provably correct critical paths, Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI, p.119-142, June 1989, Cambridge, Massachusetts, United States
	5	A. Saldanha , R. K. Brayton , A. L. Sangiovanni-Vincentelli, Equivalence of robust delay-fault and single stuck-fault test generation, Proceedings of the 29th ACM/IEEE conference on Design automation, p.173-176, June 08-12, 1992, Anaheim, California, United States
	6	Ellen Sentovich , Kanwar Jit Singh , Cho W. Moon , Hamid Savoj , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Sequential Circuit Design Using Synthesis and Optimization, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.328-333, October 11-14, 1992
	7	G. Smith. Model for delay faults based upon paths. In Proceedings of the international Test Conference, pages 342-349, August 1985.
	8	K. Wagner. The error latency of delay faults in combinational and sequential circuits, in Proceedings of the international Test Conference, pages 334-341, November 1985.

CITED BY 19

	Seiichiro Tani , Mitsuo Teramoto , Tomoo Fukazawa , Kazuyoshi Matsuhiro, Efficient Path Selection for Delay Testing Based on Path Clustering, Journal of Electronic Testing: Theory and Applications, v.15 n.1-2, p.75-85, August-October 1999
	Irith Pomeranz , Sudhakar M. Reddy, On synthesis-for-testability of combinational logic circuits, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.126-132, June 12-16, 1995, San Francisco, California, United States
	Karl Fuchs , Michael Pabst , Torsten Rössel, RESIST: a recursive test pattern generation algorithm for path delay faults, Proceedings of the conference on European design automation, p.316-321, September 19-23, 1994, Grenoble, France
	Mukund Sivaraman , Andrzej J. Strojwas, Delay fault coverage: a realistic metric and an estimation technique for distributed path delay faults, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.494-501, November 10-14, 1996, San Jose, California, United States
	U. Sparmann , D. Luxenburger , K.-T. Cheng , S. M. Reddy, Fast identification of robust dependent path delay faults, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.119-125, June 12-16, 1995, San Francisco, California, United States
	Irith Pomeranz , Sudhakar M. Reddy, Design-for-testability for path delay faults in large combinatorial circuits using test-points, Proceedings of the 31st annual conference on Design automation, p.358-364, June 06-10, 1994, San Diego, California, United States
	Michael Kishinevsky , Alex Kondratyev , Luciano Lavagno , Alexander Saldanha , Alexander Taubin, Partial scan delay fault testing of asynchronous circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.728-735, November 09-13, 1997, San Jose, California, United States
	Ramesh C. Tekumalla , Prem R. Menon, Test generation for primitive path delay faults in combinational circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.636-641, November 09-13, 1997, San Jose, California, United States
	Edward W. Y. Liu , Alberto L. Sangiovanni-Vincentelli, Nyquist data converter testing and yield analysis using behavioral simulation, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.341-348, November 07-11, 1993, Santa Clara, California, United States
	Ramesh C. Tekumalla , Prem R. Menon, On primitive fault test generation in non-scan sequential circuits, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.275-282, November 08-12, 1998, San Jose, California, United States
	Wuudiann Ke , Premachandran R. Menon, Synthesis of Delay-Verifiable Combinational Circuits, IEEE Transactions on Computers, v.44 n.2, p.213-222, February 1995
	Huawei Li , Zhongcheng Li , Yinghua Min, Reduction of Number of Paths to be Tested in Delay Testing, Journal of Electronic Testing: Theory and Applications, v.16 n.5, p.477-485, Oct 2000
	Irith Pomeranz , Sudhakar M. Reddy, On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits, IEEE Transactions on Computers, v.45 n.1, p.50-62, January 1996
	Irith Pomeranz , Sudhakar M. Reddy, Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.5, p.679-689, October 2001
	Ramesh C. Tekumalla , Premachandran R. Menon, On Redundant Path Delay Faults in Synchronous Sequential Circuits, IEEE Transactions on Computers, v.49 n.3, p.277-282, March 2000
	Marwan A. Gharaybeh , Michael L. Bushnell , Vishwani D. Agrawal, Classification and Test Generation for Path-Delay FaultsUsing Single Struck-at Fault Tests, Journal of Electronic Testing: Theory and Applications, v.11 n.1, p.55-67, Aug. 1997
	Angela Krstic , Kwang-Ting Cheng, Resynthesis of Combinational Circuts for Path Count Reduction and for Path Delay Fault Testability, Proceedings of the 1996 European conference on Design and Test, p.486, March 11-14, 1996
	Bernd Becker , Rolf Drechsler , Rolf Krieger , Sudhakar M. Reddy, A Fast Optimal Robust Path Delay Fault Testable Adder, Proceedings of the 1996 European conference on Design and Test, p.491, March 11-14, 1996
	Ying-Yen Chen , Jing-Jia Liou, Diagnosis framework for locating failed segments of path delay faults, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.6, p.755-765, June 2008