High-level synthesis of fault-secure microarchitectures

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High-level synthesis of fault-secure microarchitectures

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 429 - 433

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

Ramesh Karri
Alex Orailoğlu

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 12, Citation Count: 5

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Prithviraj Banerjee , Jacob A. Abraham, Fault-secure algorithms for multiple-processor systems, Proceedings of the 11th annual international symposium on Computer architecture, p.279-287, January 1984
	2	Daniel D. Gajski , Nikil D. Dutt , Allen C.-H. Wu , Steve Y.-L. Lin, High-level synthesis: introduction to chip and system design, Kluwer Academic Publishers, Norwell, MA, 1992
	3	D. Gu, D. J. Rosenkrantz, and S. S. Ravi. Construction and Analysis of Fault-Secure Multiprocessor Schedules. In Proc of ~ist FTCS, pp 120-127, 1991.
	4	R. Karri and A. Orailo~lu. High-Level Synthesis of Fault-Secure Microarchitectures. Tech. Rep. 267, UCSD, Dept. of CSE, October 1992.
	5	R. Karri and A. Orailo~lu. Scheduling with Rollback Constraints in High-Level Synthesis of Self-Recovering ASICs. In Proc FTCS, pp 519-526, July 1992.
	6	R. Karri , A. Orailoglu, Transformation-based high-level synthesis of fault-tolerant ASICs, Proceedings of the 29th ACM/IEEE conference on Design automation, p.662-665, June 08-12, 1992, Anaheim, California, United States
	7	Parag K. Lala, Fault tolerant and fault testable hardware design, Prentice-Hall, Inc., Upper Saddle River, NJ, 1985
	8	M. C. McFarland, A. C. Parker, and R. Camposano. The High-Level Synthesis of Digital Systems. Proc of IEEE, 78(2):301-318_, February 1990.
	9	Christos A. Papachristou , Scott Chiu , Haidar Harmanani, A data path synthesis method for self-testable designs, Proceedings of the 28th conference on ACM/IEEE design automation, p.378-384, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127698]
	10	N.Park and A. C. Parker. A software package for synthesis of pipelines from behavioral specifications. IEEE Trans on CAD, 7(3):356-370, March 1988.
	11	P. G. Paulin and J. P. Knight. Force-directed scheduling for the behavioral synthesis of ASICs. IEEE Trans on CAD, 8(6):661-679, June 1989.
	12	D. P. Siewiorek. Architecture of Fault-Tolerant Computers: An Historical Perspective. Proc of IEEE, 79(12):1710-1734, December 1991.

CITED BY 5

	Balakrishnan Iyer , Ramesh Karri, Introspection: a low overhead binding technique during self-diagnosing microarchitecture synthesis, Proceedings of the 33rd annual conference on Design automation, p.137-142, June 03-07, 1996, Las Vegas, Nevada, United States
	C. Bolchini , W. Fornaciari , F. Salice , D. Sciuto, Concurrent error detection at architectural level, Proceedings of the 11th international symposium on System synthesis, p.72-75, December 02-04, 1998, Hsinchu, Taiwan, China
	Ganesh Lakshminarayana , Anand Raghunathan , Niraj K. Jha, Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis, IEEE Transactions on Computers, v.49 n.9, p.865-885, September 2000
	Vinu Vijay Kumar , John Lach, Highly flexible multi-mode system synthesis, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 19-21, 2005, Jersey City, NJ, USA
	Vinu Vijay Kumar , John Lach, Highly flexible multimode digital signal processing systems using adaptable components and controllers, EURASIP Journal on Applied Signal Processing, v.2006 n.1, p.73-73, 01 January