An approach for redesigning in data path synthesis

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An approach for redesigning in data path synthesis

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 419 - 423

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

Christos Papachristou
Haidar Harmanani
Mehrdad Nourani

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 7, Downloads (12 Months): 7, Citation Count: 2

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Xinghao Chen , Michael L. Bushnell, A module area estimator for VLSI layout, Proceedings of the 25th ACM/IEEE conference on Design automation, p.54-59, June 12-15, 1988, Atlantic City, New Jersey, United States
	2	M. Fujita, T. Kakuda, " A Redesign Approach to High-Level Synthesis," High-Level Synthesis Workshop, 1991.
	3	D. Knapp, "Manual Rescheduling and Incremental Repair of Register-Level Datapaths," Proc. o} the ICCAD, 1989.
	4	David W. Knapp, Datapath optimization using feedback, Proceedings of the conference on European design automation, February 25-28, 1991, Amsterdam, The Netherlands
	5	F. J. Kurdahi and A. C. Parker, " Techniques for Area Estimation of VLSI Layouts," IEEE Trans. on CAD, January 1989.
	6	M. McFarland, A. Parker, and R. Composano, "The High Level Synthesis of Digital Systems," IEEE Trans. on CAD, February 1990, pp. 301-318.
	7	Mehrdad Nourani , Christos Papachristou, A layout estimation algorithm for RTL datapaths, Proceedings of the 30th international conference on Design automation, p.285-291, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164895]
	8	H. Harmanani , C. Papachristou , S. Chiu , M. Nourani, SYNTEST: an environment for system-level design for test, Proceedings of the conference on European design automation, p.402-407, November 1992, Congress Centrum Hamburg, Hamburg, Germany
	9	P. G. Paulin , J. P. Knight, Force-directed scheduling in automatic data path synthesis, Proceedings of the 24th ACM/IEEE conference on Design automation, p.195-202, June 28-July 01, 1987, Miami Beach, Florida, United States [doi>10.1145/37888.37918]
	10	K. Ueda, H. Kitazawa et al., " Chip Floor Plan for Hierarchical VLSI Layout Design," IEEE Trans. on CAD, January 1985.
	11	Jen-Pin Weng , Alice C. Parker, 3D scheduling: high-level synthesis with floorplanning, Proceedings of the 28th conference on ACM/IEEE design automation, p.668-673, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127748]

CITED BY 2

	Wei Zhao , Christos A. Papachristou, Synthesis of reusable DSP cores based on multiple behaviors, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.103-108, November 10-14, 1996, San Jose, California, United States
	Chris Papachristou , Yusuf Alzazeri, A method of distributed controller design for RTL circuits, Proceedings of the conference on Design, automation and test in Europe, p.48-es, January 1999, Munich, Germany