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Resolving signal correlations for estimating maximum currents in CMOS combinational circuits
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents
Dallas, Texas, United States
Pages: 384 - 388  
Year of Publication: 1993
ISBN:0-89791-577-1
Authors
Harish Kriplani
Farid Najm
Ping Yang
Ibrahim Hajj
Sponsors
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 6,   Downloads (12 Months): 9,   Citation Count: 10
Additional Information:

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
H. Kriplani , F. Najm , I. Hajj, Maximum current estimation in CMOS circuits, Proceedings of the 29th ACM/IEEE conference on Design automation, p.2-7, June 08-12, 1992, Anaheim, California, United States
 
2
Carver Mead , Lynn Conway, Introduction to VLSI Systems, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1979
 
3
Michael R. Garey , David S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, W. H. Freeman & Co., New York, NY, 1979
 
4
S. Kirkpatrick, C. D. Gelatt, Jr., and M. P. Vecchi, "Optimization by simulated annealing," Science, vol. 220, no. 4598, pp. 671-680, 13 May 1983.
 
5
Judea Pearl, Heuristics: intelligent search strategies for computer problem solving, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1984
 
6
F. Brglez and H. Fujiwara, "A neutral netlist of 10 combinational benchmark circuits and a target translator in fortran," in Proceedings of International Symposium on Circuits and Systems, pp. 695-698, June 1985.
 
7
F. Brglez, D. Bryan, and K. Kogmifiski, "Combinational profiles of sequential benchmark circuits," in Proceedings of International Symposium on Circuits and Systems, pp. 1929-1934, May 1989.

CITED BY  10
Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel, K2: an estimator for peak sustainable power of VLSI circuits, Proceedings of the 1997 international symposium on Low power electronics and design, p.178-183, August 18-20, 1997, Monterey, California, United States
Rajat Chaudhry , David Blaauw , Rajendran Panda , Tim Edwards, Current signature compression for IR-drop analysis, Proceedings of the 37th conference on Design automation, p.162-167, June 05-09, 2000, Los Angeles, California, United States
Fei Li , Lei He, Maximum current estimation considering power gating, Proceedings of the 2001 international symposium on Physical design, p.106-111, April 01-04, 2001, Sonoma, California, United States
Chuan-Yu Wang , Kaushik Roy, COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.52-55, November 09-13, 1997, San Jose, California, United States
Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel, Effects of delay models on peak power estimation of VLSI sequential circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.45-51, November 09-13, 1997, San Jose, California, United States
S. Bobba , I. N. Hajj, Estimation of maximum current envelope for power bus analysis and design, Proceedings of the 1998 international symposium on Physical design, p.141-146, April 06-08, 1998, Monterey, California, United States
Hratch Mangassarian , Andreas Veneris , Sean Safarpour , Farid N. Najm , Magdy S. Abadir, Maximum circuit activity estimation using pseudo-boolean satisfiability, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
Michael S. Hsiao, Peak power estimation using genetic spot optimization for large VLSI circuits, Proceedings of the conference on Design, automation and test in Europe, p.38-es, January 1999, Munich, Germany
Aman A. Kokrady , C. P. Ravikumar, Static Verification of Test Vectors for IR Drop Failure, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.760, November 09-13, 2003
J. Zejda , E. Cerny , S. Shenoy , N. C. Rumin, Bounding Switching Activity in CMOS Circuits Using Constraint Resolution, Proceedings of the 1996 European conference on Design and Test, p.294, March 11-14, 1996

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.1 Design Styles
          Subjects: Combinational logic
  B.7 INTEGRATED CIRCUITS


General Terms:
Algorithms, Design, Experimentation, Performance, Reliability

Collaborative Colleagues:
Harish Kriplani: colleagues
Farid Najm: colleagues
Ping Yang: colleagues
Ibrahim Hajj: colleagues

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