Performance enhancement of CMOS VLSI circuits by transistor reordering

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Performance enhancement of CMOS VLSI circuits by transistor reordering

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 361 - 366

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

Bradley S. Carlson
C. Y. Roger Chen

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 11, Citation Count: 5

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	M.C. Chang and C.F. Chen. "PROMPT3- A Cell-Based Transistor Sizing Program Using Heuristic and Simulated Annealing Algorithms". In Proc. of CICC, pages 17.2.1 - 17.2.4, 1989.
	2	H.Y. Chen and S.M. Kang. "iCOACH" A Circuit Optimization Aid for CMOS High-Performance Circuits". In Proc. of ICCAD, pages 372-375, 1988.
	3	J.P. Fishburn and A.E. Dunlop. "TILOS: A PosynomiaJ Programming Approach to Transistor Sizing". In Proc. of ICCAD, pages 326-328, 1985.
	4	K. S. Hedlund, Aesop: a tool for automated transistor sizing, Proceedings of the 24th ACM/IEEE conference on Design automation, p.114-120, June 28-July 01, 1987, Miami Beach, Florida, United States [doi>10.1145/37888.37905]
	5	William H. Kao , Nader Fathi , Chia-Hao Lee, Algorithms for automatic transistor sizing in CMOS digital circuits, Proceedings of the 22nd ACM/IEEE conference on Design automation, p.781-784, June 1985, Las Vegas, Nevada, United States [doi>10.1145/317825.317991]
	6	D.P. Marple and A.E. Carnal. "Optimal Selection of Transistor Sizes in Digital VLSI Circuits". In Stanford Conference on Advanced Research in VLSI, pages 151-172, 1987.
	7	Jonathan D. Pincus , Alvin M. Despain, Delay reduction using simulated annealing, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.690-695, July 1986, Las Vegas, Nevada, United States
	8	J.M. Shyu, A. Sangiovanni-Vincentelli, J.P. Fishburn, and A.E. Dunlop. "Optimization-Based Transistor Sizing". IEEE J. of SS Circ., 23(2):400-409, April 1988.
	9	B.S. Carlson and C.Y.R. Chen. "Effects of Transistor Reordering on the Performance of MOS Digital Circuits". In Proc. of Mid. Symp. on Circ. and Sys., 1992.
	10	H.Y. Chen and S. Dutta. "A Timing Model for Static CMOS Gates". In Proc. of ICCAD, pages 72-75, 1989.
	11	T. Sakurai and A.R. Newton. "Delay Analysis of Series- Connected M OSFET Circuits". IEEE J. of SS Circ., 26(2):122-131, February 1991.
	12	D. Deschacht, M. Robert, and D. Auvergne. "Synchronous Mode Evaluation of Delays in CMOS Structures". IEEE J. of SS Circ., 26(5):789-795, May 1991.
	13	M. Marek-Sadowska and S.P. Lin. "Pin Assignment for Improved Performance in Standard Cell Design". In Proc. of ICCD, pages 339-342, 1990.
	14	A.E. Dunlop, J.P. Fishburn, D.D. Hill, and D.D. Shugard. "Experiments Using Automatic Physical Design Techniques for Optimizing Circuit Performance". In Proc. of ISCAS, pages 847-851, 1990.
	15	B.S. Carlson, C.Y.R. Chen, and U. Singh. "Optimal Cell Generation for Dual Independent Layout Styles". IEEE Tran. on CAD of ICAS, 10(6):770-782, June 1991.

CITED BY 5

	S. C. Prasad , K. Roy, Transistor reordering for power minimization under delay constraint, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.2, p.280-300, April 1996
	Martin Lefebvre , David Marple , Carl Sechen, The future of custom cell generation in physical synthesis, Proceedings of the 34th annual conference on Design automation, p.446-451, June 09-13, 1997, Anaheim, California, United States
	Alexey L. Glebov , David Blaauw , Larry G. Jones, Transistor reordering for low power CMOS gates using an SP-BDD representation, Proceedings of the 1995 international symposium on Low power design, p.161-166, April 23-26, 1995, Dana Point, California, United States
	Michael J. Alexander, Power optimization for FPGA look-up tables, Proceedings of the 1997 international symposium on Physical design, p.156-162, April 14-16, 1997, Napa Valley, California, United States
	Enric Musoll , Jordi Cortadella, Optimizing CMOS Circuits for Low Power Using Transistor Reordering, Proceedings of the 1996 European conference on Design and Test, p.219, March 11-14, 1996