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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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P. Dewilde, E. Deprettere, and R. Nouta, "Parallel and pipelined VLSI implementation of signal processing algorithms", pp. 257-276, VLSI and modern ssgnal processing, S. Y. Kung, H. J. Whitehouse, T. Kailath, editors, Prentice-hall, 1985.
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D. Gajski, "An Algorithm for Solving Linear Recurrence Systems on Parallel and Pipelined Machines", IEEE Transactions on Computers, Vol. c-30, No.3, March 1981.
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G. Goossens , J. Vandewlle , H. De Man, Loop optimization in register-transfer scheduling for DSP-systems, Proceedings of the 26th ACM/IEEE conference on Design automation, p.826-831, June 25-28, 1989, Las Vegas, Nevada, United States
[doi> 10.1145/74382.74384]
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R. Hartley and A. Casavant, "Tree height minimization in pipelined architectures", Proceedings of 1989 IEEE International Conference on CAD, Santa Clara, California, November 1989.
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Cheng-Tsung Hwang , Yu-Chin Hsu , Youn-Long Lin, Scheduling for functional pipelining and loop winding, Proceedings of the 28th conference on ACM/IEEE design automation, p.764-769, June 17-22, 1991, San Francisco, California, United States
[doi> 10.1145/127601.127766]
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Proceedings of IEEE Malta-Chip Module Conference, Santa Cruz, California, 1992.
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R Nouta, a personal correspondence with the authors, Technical University of Delft, October, 1992.
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Roni Potasman , Joseph Lis , Alexandru Nicolau , Daniel Gajski, Percolation based synthesis, Proceedings of the 27th ACM/IEEE conference on Design automation, p.444-449, June 24-27, 1990, Orlando, Florida, United States
[doi> 10.1145/123186.123333]
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N.K. Tsao, "Solving triangular system in parallel is accurate", pp. 633-638~ Nurnar, val L,near Algvbra~ Dig,$al Signal Processsng and Parallel A lgorathms, Edited by Gene Golub and Paul Van Dooren, NATO Series F: Computer and Systems Sciences, Vol. 70, Springer-Verlag, 1991.
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H. Wang, N. Dutt, A. Nicolau and K. S. Siu "High-level synthesis of scalable architectures for IIR filters using multi-chip modules", UCI ICS TR 92-104, October 1992.
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