On routability prediction for field-programmable gate arrays

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On routability prediction for field-programmable gate arrays

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 326 - 330

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

Pak K. Chan
Martine D. F. Schlag
Jason Y. Zien

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 11, Downloads (12 Months): 25, Citation Count: 22

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	XILINX:The Programmable Gate Array Data Book. 2100 Logic Drive, San Jose, CA 95124, 1992.
	2	Stephen D. Brown , Robert J. Francis , Jonathan Rose , Zvonko G. Vranesic, Field-programmable gate arrays, Kluwer Academic Publishers, Norwell, MA, 1992
	3	K. A. E1-Ayat, A. E1 Gamal, R. Guo, J. Chang, R. K. Mak, F. Chiu, E. Z. Hamdy, J. McCollum, and A. Mohsen. A CMOS electrically configurable gate array. IEEE JSSC, 24(3):752-762, June 1989.
	4	A. El Gamal. Two-Dimensional Stochastic Model for Interconnections in Master Slice Integrated Circuits. IEEE Trans CAS, 28(2):127-138, Feb. 1981.
	5	M. Feuer. Connectivity of Random Logic. IEEE TC, C-31(1):29-33, Jan. 1982.
	6	T. Hamada , C.-K. Cheng , P. M. Chau, A wire length estimation technique utilizing neighborhood density equations, Proceedings of the 29th ACM/IEEE conference on Design automation, p.57-61, June 08-12, 1992, Anaheim, California, United States
	7	D. Hill and N.-S. Woo. The benefits of flexibility in look-up table FPGAs. In Proc. of Intl. Workshop on Field Programmable Logic and Applications, Oxford, England, Sept. 1991.
	8	F. Kurdahi and A. C. Parker. Rent's rule and average wire length in standard cell layouts. Unpublished manuscript, Dec. 1989.
	9	B. Osann and A. El Gamal. Compare ASIC capacities with gate array benchmarks. Electronic Design, Oct. 1988.
	10	M. Pedram and B. Preas. Interconnection length estimation for optimized standard cell layouts. IEEE ICCAD 89, pg.390-393, Nov. 1989.
	11	Quickturn Systems Inc. 325 East Middlefield Road, Mountain View, CA 94043, 1991.
	12	S. Sa~try and A. C. Parker. Stochastic Models for Wireability Analysis of Gate Arrays. IEEE Trans. on CAD, CAD-5(1):52-65, Jan. 1986.
	13	Martine D. F. Schlag , Jackson Kong , Pak K. Chan, Routability-Driven Techology Mapping for LookUp-Table-Based FPGAs, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.86-90, October 11-14, 1992

CITED BY 22

	Sudip K. Nag , Rob A. Rutenbar, Performance-driven simultaneous place and route for island-style FPGAs, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.332-338, November 05-09, 1995, San Jose, California, United States
	Jason Cong , Yuzheng Ding, Combinational logic synthesis for LUT based field programmable gate arrays, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.2, p.145-204, April 1996
	Parivallal Kannan , Shankar Balachandran , Dinesh Bhatia, On metrics for comparing routability estimation methods for FPGAs, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Sudip K. Nag , Rob A. Rutenbar, Performance-driven simultaneous place and route for row-based FPGAs, Proceedings of the 31st annual conference on Design automation, p.301-307, June 06-10, 1994, San Diego, California, United States
	Joel Darnauer , Wayne Wei-Ming Dai, A method for generating random circuits and its application to routability measurement, Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays, p.66-72, February 11-13, 1996, Monterey, California, United States
	Kusnadi , Jo Dale Carothers, A method of measuring nets routability for MCM's general area routing problems, Proceedings of the 1999 international symposium on Physical design, p.186-192, April 12-14, 1999, Monterey, California, United States
	G. Parthasarathy , M. Marek-Sadowska , Arindam Mukherjee , Amit Singh, Interconnect complexity-aware FPGA placement using Rent's rule, Proceedings of the 2001 international workshop on System-level interconnect prediction, p.115-121, March 31-April 01, 2001, Sonoma, California, United States
	Arifur Rahman , Shamik Das , Anantha Chandraksan , Rafael Reif, Wiring requirement and three-dimensional integration of field-programmable gate arrays, Proceedings of the 2001 international workshop on System-level interconnect prediction, p.107-113, March 31-April 01, 2001, Sonoma, California, United States
	H.-G. Martin , W. Rosenstiel, A comparing study of technology mapping for FPGA, Proceedings of the conference on Design, automation and test in Europe, p.939-940, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Gi-Joon Nam , Karem A. Sakallah , Rob A. Rutenbar, Satisfiability-based layout revisited: detailed routing of complex FPGAs via search-based Boolean SAT, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.167-175, February 21-23, 1999, Monterey, California, United States
	R. Glenn Wood , Rob A. Rutenbar, FPGA routing and routability estimation via Boolean satisfiability, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.119-125, February 09-11, 1997, Monterey, California, United States
	Michael Hutton, Interconnect prediction for programmable logic devices, Proceedings of the 2001 international workshop on System-level interconnect prediction, p.125-131, March 31-April 01, 2001, Sonoma, California, United States
	Michael J. Alexander , James P. Cohoon , Joseph L. Ganley , Gabriel Robins, An architecture-independent approach to FPGA routing based on multi-weighted graphs, Proceedings of the conference on European design automation, p.259-264, September 19-23, 1994, Grenoble, France
	Gi-Joon Nam , Fadi Aloul , Karem Sakallah , Rob Rutenbar, A comparative study of two Boolean formulations of FPGA detailed routing constraints, Proceedings of the 2001 international symposium on Physical design, p.222-227, April 01-04, 2001, Sonoma, California, United States
	Arifur Rahman , Shamik Das , Anantha P. Chandrakasan , Rafael Reif, Wiring requirement and three-dimensional integration technology for field programmable gate arrays, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.1, p.44-54, February 2003
	Grant Wigley , David Kearney, The management of applications for reconfigurable computing using an operating system, Australian Computer Science Communications, v.24 n.3, p.73-81, January-February 2002
	Amit Singh , Ganapathy Parthasarathy , Malgorzata Marek-Sadowska, Interconnect resource-aware placement for hierarchical FPGAs, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Pak K. Chan , Martine D. F. Schlag , Jason Y. Zien, Spectral-based multi-way FPGA partitioning, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.133-139, February 12-14, 1995, Monterey, California, United States
	Amit Singh , Ganapathy Parthasarathy , Malgorzata Marek-Sadowska, Efficient circuit clustering for area and power reduction in FPGAs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.7 n.4, p.643-663, October 2002
	Joachim Pistorius , Mike Hutton, Placement rent exponent calculation methods, temporal behaviour and FPGA architecture evaluation, Proceedings of the 2003 international workshop on System-level interconnect prediction, April 05-06, 2003, Monterey, CA, USA
	Parivallal Kannan , Shankar Balachandran , Dinesh Bhatia, On metrics for comparing interconnect estimation methods for FPGAs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.4, p.381-385, April 2004
	Wei Mark Fang , Jonathan Rose, Modeling routing demand for early-stage FPGA architecture development, Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays, February 24-26, 2008, Monterey, California, USA