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 REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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M. Marek-Sadowska and S. P. Lin, "Timing Driven Placement," Proc. of ICCAD, 1989, pp. 94-97.
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Wilm E. Donath , Reini J. Norman , Bhuwan K. Agrawal , Stephen E. Bello , Sang Yong Han , Jerome M. Kurtzberg , Paul Lowy , Roger I. McMillan, Timing driven placement using complete path delays, Proceedings of the 27th ACM/IEEE conference on Design automation, p.84-89, June 24-27, 1990, Orlando, Florida, United States
[doi> 10.1145/123186.123232]
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C. Sechen and A. Sangiovanni-Vincentelli, "The TimberWolf Placement and Routing Package," IEEE Custom Integrated Cicuits Conf., 1984.
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R. Rao, "A Global Router for Channelled FP- GAs," MCNC i, ogic Syuthesis Workshop, 1992, pp. 119-129.
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A.E. Gamma} et. al., "An Architecture for Electrically Configurable Gate Array," IEEE Journal of Solid S~a~e Circuits, Vol. 24, No. 2, pp. 394-398, April 1989.
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K. Roy and :I. Abraham, "The Use of RTL Descriptions in Accurate Timing Verification and Test Generation , IEEE Journal o} Solid S~ate Circuits, September, 1991.
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B. Kernighan and S. Lin, "An Efficient Heuristic Procedure for Partitioning Graphs", Bell Sys Tech Journal, vol 49, no. 2, pp. 291-307, 2/70.
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