Cost minimization of partitions into multiple devices

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Cost minimization of partitions into multiple devices

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 315 - 320

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

Roman Kužnar
Franc Brglez
Krzysztof Kozminski

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 8, Citation Count: 22

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	W.E.Donath. Logic Partitioning. in Physical Design Automation of VLSI Systems , B. Preas and M. Lorenzetti, Ed. The Benjamin/Cummings Publisher Company, Menlo Park, California 94025, 1988.
	2	L. A. Sanchis, Multiple-Way Network Partitioning, IEEE Transactions on Computers, v.38 n.1, p.62-81, January 1989 [doi>10.1109/12.8730]
	3	Ching-Wei Yeh , Chung-Kuan Cheng , Ting-Ting Y. Lin, A general purpose multiple way partitioning algorithm, Proceedings of the 28th conference on ACM/IEEE design automation, p.421-426, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127706]
	4	R. Kuznar, F. Brglez, and K. Kozminski. Partitioning Digital Circuits for Implementation in Multiple FPCA ICs. Technical Report TR93-03, MCNC, Research Triangle Park, NC, March 1993.
	5	The Programmable Gate Array Data Book. Xilinx, Inc., 2100 Logic Drive, San Jose, California, 1991.
	6	Xilinx FPGA price quotation. Sept 1992.
	7	C. M. Fiduccia , R. M. Mattheyses, A linear-time heuristic for improving network partitions, Proceedings of the 19th conference on Design automation, p.175-181, January 1982
	8	F. Brglez and H. Fujiwara. A Neutral Netlist of 10 Combinational Benchmark Circuits and A Target Translator in FORTRAN. June 1985. (prepared for the participants in the Special Session on Gate-Level ATPG in IEEE 1985 Intl. Symp. On Circuits and Systems).
	9	F. Brglez, D. Bryan, and K. Kozminski. Combinational Profiles of Sequential Benchmark Circuits. In Proc. of IEEE 1989 Intl. Symp. on Circuits and Systems, May 1989.

CITED BY 22

	Sudip K. Nag , Rob A. Rutenbar, Performance-driven simultaneous place and route for row-based FPGAs, Proceedings of the 31st annual conference on Design automation, p.301-307, June 06-10, 1994, San Diego, California, United States
	Pak K. Chan , Martine D. F. Schlag , Jason Y. Zien, Spectral-based multi-way FPGA partitioning, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.133-139, February 12-14, 1995, Monterey, California, United States
	Dennis J.-H. Huang , Andrew B. Kahng, Multi-way system partitioning into a single type or multiple types of FPGAs, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.140-145, February 12-14, 1995, Monterey, California, United States
	Roman Kužnar , Franc Brglez , Baldomir Zajc, Multi-way netlist partitioning into heterogeneous FPGAs and minimization of total device cost and interconnect, Proceedings of the 31st annual conference on Design automation, p.238-243, June 06-10, 1994, San Diego, California, United States
	Roman Kužnar , Baldomir Zajc , Franc Brglez, A unified cost model for min-cut partitioning with replication applied to optimization of large heterogeneous FPGA partitions, Proceedings of the conference on European design automation, p.271-276, September 19-23, 1994, Grenoble, France
	Sverre Wichlund, On multilevel circuit partitioning, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.505-511, November 08-12, 1998, San Jose, California, United States
	Roman Kužnar , Franc Brglez, PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.644-649, November 05-09, 1995, San Jose, California, United States
	Ke Zhong , Shantanu Dutt, Algorithms for simultaneous satisfaction of multiple constraints and objective optimization in a placement flow with application to congestion control, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Shantanu Dutt , Wenyong Deng, Cluster-aware iterative improvement techniques for partitioning large VLSI circuits, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.7 n.1, p.91-121, January 2002
	Prashant Sawkar , Donald Thomas, Multi-way partitioning for minimum delay for look-up table based FPGAs, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.201-210, June 12-16, 1995, San Francisco, California, United States
	Joachim Pistorius , Edmée Legai , Michel Minoux, Generation of very large circuits to benchmark the partitioning of FPGA, Proceedings of the 1999 international symposium on Physical design, p.67-73, April 12-14, 1999, Monterey, California, United States
	U. Ober , M. Glesner, Multiway netlist partitioning onto FPGA-based board architecture, Proceedings of the conference on European design automation, p.150-155, September 18-22, 1995, Brighton, England
	Wen-Jong Fang , Allen C.-H. Wu, Multi-way FPGA partitioning by fully exploiting design hierarchy, Proceedings of the 34th annual conference on Design automation, p.518-521, June 09-13, 1997, Anaheim, California, United States
	Huiqun Liu , D. F. Wong, Network flow based multi-way partitioning with area and pin constraints, Proceedings of the 1997 international symposium on Physical design, p.12-17, April 14-16, 1997, Napa Valley, California, United States
	Wen-Jong Fang , Allen C.-H. Wu, Multiway FPGA partitioning by fully exploiting design hierarchy, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.1, p.34-50, Jan. 2000
	Nan-Chi Chou , Lung-Tien Liu , Chung-Kuan Cheng , Wei-Jin Dai , Rodney Lindelof, Circuit partitioning for huge logic emulation systems, Proceedings of the 31st annual conference on Design automation, p.244-249, June 06-10, 1994, San Diego, California, United States
	Ulrich Weinmann , Oliver Bringmann , Wolfgang Rosenstiel, Device selection for system partitioning, Proceedings of the conference on European design automation, p.2-7, September 18-22, 1995, Brighton, England
	Shantanu Dutt , Halim Theny, Partitioning around roadblocks: tackling constraints with intermediate relaxations, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.350-355, November 09-13, 1997, San Jose, California, United States
	Helena Krupnova , Gabriele Saucier, Iterative improvement based multi-way netlist partitioning for FPGAs, Proceedings of the conference on Design, automation and test in Europe, p.117-es, January 1999, Munich, Germany
	H.-J. Herpel , M. Glesner, Rapid Prototyping of Real-Time Information Processing Unitsfor Mechatronic Systems, Real-Time Systems, v.14 n.3, p.269-291, May 1, 1998
	M. H. C. Lee , D. L. Tao, A testability measure for hierarchical design environments, Proceedings of the 1995 European conference on Design and Test, p.303, March 06-09, 1995
	Rajarshi Mukherjee , Song Liu , Seda Ogrenci Memik , Somsubhra Mondal, A high-level clustering algorithm targeting dual V_dd FPGAs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.4, p.1-20, September 2008