Utilization of multiport memories in data path synthesis

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Utilization of multiport memories in data path synthesis

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 298 - 302

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

Taewhan Kim
C. L. Liu

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 16, Citation Count: 16

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	M. C. McFarland, A. C. Parker and R. Camposano, "The High-level Synthesis of Digital Systems," Proc. IEEE, vol: 78, no. 2, pp.301-318, 1990.
	2	Daniel D. Gajski , Nikil D. Dutt , Allen C.-H. Wu , Steve Y.-L. Lin, High-level synthesis: introduction to chip and system design, Kluwer Academic Publishers, Norwell, MA, 1992
	3	C.-J. Tseng and D. P. Siewiorek, "Automated Synthesis of Data Paths in Digital Systems," IEEE Trans. CAD, vol: CAD-5, no. 3, pp.379-395, July 1986.
	4	Peter Marwedel, The mimola design system: Tools for the design of digital processors, Proceedings of the 21st conference on Design automation, p.587-593, June 25-27, 1984, Albuquerque, New Mexico, United States
	5	L. Stok, Interconnect optimisation during data path allocation, Proceedings of the conference on European design automation, March 12-15, 1990, Glasgow, Scotland
	6	M. Balakrishnan et al., "Allocation of Multiport Memories in Data Path Synthesis," IEEE Trans. CAD, vol. 7, no. 4; pp.536~540, April 1988.
	7	I. Abroad and C. Y. Roger Chen, "Post-Process for Data Path Synthesis using Multiport Memories," Proc. IC- CAD'91, pp.276-279, 1991.
	8	F. J. Kurdahi , A. C. Parker, REAL: a program for REgister ALlocation, Proceedings of the 24th ACM/IEEE conference on Design automation, p.210-215, June 28-July 01, 1987, Miami Beach, Florida, United States [doi>10.1145/37888.37920]
	9	E. G. Coffman et al. "Approximation Algorithms for Bin- Packing - An Updated Survey" in Algorithm Design for Computer System Design, M. Luccertini, G. Auslello and P. Serafiri, Springer Verlag, pp.49-106, 1984.
	10	M. R. Garey, R. L. Graham, D. S. Johnson and A. C. Yao; "Resource Constrained Scheduling as Generalized Bin Packing," J. Combinatorial Theory, Set. A21, pp.257-298, 1976.
	11	Chu-Yi Huang , Yen-Shen Chen , Youn-Long Lin , Yu-Chin Hsu, Data path allocation based on bipartite weighted matching, Proceedings of the 27th ACM/IEEE conference on Design automation, p.499-504, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123350]
	12	C. A. Papachristou , H. Konuk, A linear program driven scheduling and allocation method followed by an interconnect optimization algorithm, Proceedings of the 27th ACM/IEEE conference on Design automation, p.77-83, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123231]
	13	P. G. Paulin and J. P. Knight, "High-Level Synthesis Benchmark Results using a Global Scheduling Algorithm" in Logic and Architecture Synthesis for Silicon Compilers, North- Holland, pp. 211-228, 1989.
	14	F. S. Tsai and Y. C. Hsu, "Data Path Construction and Refinement," Pr0c. ICCAD'90, pp.308-311, 1990.
	15	B. S. Haroun and M. I. Elmasry, "Architecture Synthesis for DSP Silicon Compiler," IEEE Trans. CAD, vol. CAD-8, no. 4, pp.431-447, April 1989.

CITED BY 16

	I. Ouaiss , R. Vemuri, Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers, Proceedings of the conference on Design, automation and test in Europe, p.650-657, March 2001, Munich, Germany
	David J. Kolson , Alexandru Nicolau , Nikil Dutt , Ken Kennedy, Optimal register assignment to loops for embedded code generation, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.2, p.251-279, April 1996
	David J. Kolson , Alexandru Nicolau , Nikil Dutt , Ken Kennedy, Optimal register assignment to loops for embedded code generation, Proceedings of the 8th international symposium on System synthesis, p.42-47, September 13-15, 1995, Cannes, France
	Herman Schmit , Donald E. Thomas, Array mapping in behavioral synthesis, Proceedings of the 8th international symposium on System synthesis, p.90-95, September 13-15, 1995, Cannes, France
	P. R. Panda , F. Catthoor , N. D. Dutt , K. Danckaert , E. Brockmeyer , C. Kulkarni , A. Vandercappelle , P. G. Kjeldsberg, Data and memory optimization techniques for embedded systems, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.2, p.149-206, April 2001
	Pradip K. Jha , Nikil D. Dutt, High-level library mapping for memories, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.3, p.566-603, July 2000
	Preeti Ranjan Panda , Nikil D. Dutt , Alexandru Nicolau, Exploiting off-chip memory access modes in high-level synthesis, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.333-340, November 09-13, 1997, San Jose, California, United States
	Kyumyung Choi , Steven P. Levitan, A flexible datapath allocation method for architectural synthesis, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.4 n.4, p.376-404, Oct. 1999
	Preeti Ranjan Panda , Lakshmikantam Chitturi, An energy-conscious algorithm for memory port allocation, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.572-576, November 10-14, 2002, San Jose, California
	Kamal S. Khouri , Ganesh Lakshminarayana , Niraj K. Jha, Memory binding for performance optimization of control-flow intensive behaviors, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.482-488, November 07-11, 1999, San Jose, California, United States
	David J. Kolson , Alexandru Nicolau , Nikil Dutt, Minimization of memory traffic in high-level synthesis, Proceedings of the 31st annual conference on Design automation, p.149-154, June 06-10, 1994, San Diego, California, United States
	Preeti Ranjan Panda , Nikil D. Dutt , Alexandru Nicolau, On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.3, p.682-704, July 2000
	Kamal S. Khouri , Ganesh Lakshminarayana , Niraj K. Jha, Memory binding for performance optimization of control-flow intensive behavioral descriptions, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.5, p.513-524, May 2005
	Taemin Kim , Xun Liu, Compatibility path based binding algorithm for interconnect reduction in high level synthesis, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Pradip K. Jha , Nikil D. Dutt, Library Mapping for Memories, Proceedings of the 1997 European conference on Design and Test, p.288, March 17-20, 1997
	N. D. Holmes , D. D. Gajski, Architectural exploration for datapaths with memory hierarchy, Proceedings of the 1995 European conference on Design and Test, p.340, March 06-09, 1995