Behavioral synthesis of highly testable data paths under the non-scan and partial scan environments

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Behavioral synthesis of highly testable data paths under the non-scan and partial scan environments

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 292 - 297

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

Tien-Chien Lee
Niraj K. Jha
Wayne H. Wolf

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 10, Citation Count: 25

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	M. C. McFarland, A. C. Parker, and R. Camposano. "The high-level synthesis of digital systems". In Proc. IEEE, pp. 301-318, Feb. 1990.
	2	Tien-Chien Lee , Wayne Wolf , Niraj K. Jha , John M. Acken, Behavioral Synthesis for Easy Testability in Data Path Allocation, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.29-32, October 11-14, 1992
	3	Tien-Chien Lee , Wayne H. Wolf , Niraj K. Jha, Behavioral synthesis for easy testability in data path scheduling, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.616-619, November 1992, Santa Clara, California, United States
	4	C. H. Gebotys and M. I. Elmasry. "Integration of algorithmic VLSI synthesis with testability incorporation". In IEEE J. Solid-State Oircui~s, pp. 409-416, Apr. 1989.
	5	Christos A. Papachristou , Scott Chiu , Haidar Harmanani, A data path synthesis method for self-testable designs, Proceedings of the 28th conference on ACM/IEEE design automation, p.378-384, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127698]
	6	LaNae J. Avra, Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths, Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner, p.463-472, October 26-30, 1991
	7	A. Mujumdar, K. Saluja, and R. Jain. "Incorporating testability considerations in high-level synthesis". In Proe. FTOS, pp. 272-279, 1992.
	8	K.-T. Cheng , V. D. Agrawal, A Partial Scan Method for Sequential Circuits with Feedback, IEEE Transactions on Computers, v.39 n.4, p.544-548, April 1990 [doi>10.1109/12.54847]
	9	A. Ghosh, S. Devadas, and A. R. Newton. "Test generation for highly sequential circuits". In Proc. ICCAD, pp. 362-365, 1989.
	10	C.-J. Tseng and D. P. Siewiorek. "Automated synthesis of data paths in digital systems". In IEEE Trans. CAD, pp. 379-395, July 1986.
	11	Ellen Sentovich , Kanwar Jit Singh , Cho W. Moon , Hamid Savoj , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Sequential Circuit Design Using Synthesis and Optimization, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.328-333, October 11-14, 1992
	12	D. H. Lee and S. M. Reddy. "On determining scan flip-flops in partial-scan designs". In Proc. ICCAD, pp. 322-325, 1990.
	13	P. G. Paulin , J. P. Knight , E. F. Girczyc, HAL: a multi-paradigm approach to automatic data path synthesis, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.263-270, July 1986, Las Vegas, Nevada, United States
	14	Barry M. Pangre, Splicer: a heuristic approach to connectivity binding, Proceedings of the 25th ACM/IEEE conference on Design automation, p.536-541, June 12-15, 1988, Atlantic City, New Jersey, United States
	15	C. A. Papachristou. "Rescheduling transformations for high-level synthesis". In Proc. ISCAS, pp. 766-769, 1989.
	16	Chu-Yi Huang , Yen-Shen Chen , Youn-Long Lin , Yu-Chin Hsu, Data path allocation based on bipartite weighted matching, Proceedings of the 27th ACM/IEEE conference on Design automation, p.499-504, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123350]
	17	S. Y. Kung , Thomas Kailath , Harper J. Whitehouse, VLSI and Modern Signal Processing, Prentice Hall Professional Technical Reference, 1984

CITED BY 25

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	Haidar Harmanani , Christos A. Papachristou, An improved method for RTL synthesis with testability tradeoffs, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.30-35, November 07-11, 1993, Santa Clara, California, United States
	Miodrag Potkonjak , Sujit Dey, Optimizing resource utilization and testability using hot potato techniques, Proceedings of the 31st annual conference on Design automation, p.201-205, June 06-10, 1994, San Diego, California, United States
	Sujit Dey , Miodrag Potkonjak , Rabindra K. Roy, Exploiting hardware sharing in high-level synthesis for partial scan optimization, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.20-25, November 07-11, 1993, Santa Clara, California, United States
	Sujit Dey , Vijay Gangaram , Miodrag Potkonjak, A controller-based design-for-testability technique for controller-data path circuits, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.534-540, November 05-09, 1995, San Jose, California, United States
	Ishwar Parulkar , Sandeep Gupta , Melvin A. Breuer, Data path allocation for synthesizing RTL design with low BIST area overhead, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.395-401, June 12-16, 1995, San Francisco, California, United States
	Frank F. Hsu , Janak H. Patel, High-level variable selection for partial-scan implementation, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.79-84, November 08-12, 1998, San Jose, California, United States
	Kenneth D. Wagner , Sujit Dey, High-level synthesis for testability: a survey and perspective, Proceedings of the 33rd annual conference on Design automation, p.131-136, June 03-07, 1996, Las Vegas, Nevada, United States
	Ravibala Singh , John Knight, Concurrent testing in high-level synthesis, Proceedings of the 7th international symposium on High-level synthesis, p.96-103, May 18-20, 1994, Niagra-on-the-Lake, Ontario, Canada
	Sujit Dey , Miodrag Potkonjak, Non-scan design-for-testability of RT-level data paths, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.640-645, November 06-10, 1994, San Jose, California, United States
	Jaan Raik , Tanel Nõmmeots , Raimund Ubar, A New Testability Calculation Method to Guide RTL Test Generation, Journal of Electronic Testing: Theory and Applications, v.21 n.1, p.71-82, January 2005
	Saeed Safari , Amir Hossein Jahangir , Hadi Esmaeilzadeh, A parameterized graph-based framework for high-level test synthesis, Integration, the VLSI Journal, v.39 n.4, p.363-381, July 2006
	Soheil Aminzadeh , Saeed Safari, Co-evolutionary high-level test synthesis, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy
	Joan E. Carletta , Christos A. Papachristou, Behavioral Testability Insertion for Datapath/Controller Circuits, Journal of Electronic Testing: Theory and Applications, v.11 n.1, p.9-28, Aug. 1997
	M. L. Flottes , D. Hammad , B. Rouzeyre, Improving Testability of Non-Scan Designs during BehavioralSynthesis, Journal of Electronic Testing: Theory and Applications, v.11 n.1, p.29-42, Aug. 1997
	Sandhya Seshadri , Michael S. Hsiao, Formal Value-Range and Variable Testability Techniquesfor High-Level Design-For-Testability, Journal of Electronic Testing: Theory and Applications, v.16 n.1-2, p.131-145, Feb/April 2000
	Sujit Dey , Anand Raghunathan , Kenneth D. Wagner, Design for Testability Techniques at the Behavioraland Register-Transfer Levels, Journal of Electronic Testing: Theory and Applications, v.13 n.2, p.79-91, Oct. 1998
	Christos A. Papachristou , Mikhail Baklashov , Kowen Lai, High-Level Test Synthesis for Behavioral and Structural Designs, Journal of Electronic Testing: Theory and Applications, v.13 n.2, p.167-188, Oct. 1998
	Frank F. Hsu , Janak H. Patel, High-Level Controllability and Observability Analysis for Test Synthesis, Journal of Electronic Testing: Theory and Applications, v.13 n.2, p.93-103, Oct. 1998
	M. Nourani , C. Papachristou, Structural BIST Insertion Using Behavioral Test Analysis, Proceedings of the 1997 European conference on Design and Test, p.64, March 17-20, 1997
	Subhrajit Bhattacharya , Sujit Dey , Bhaskar Sengupta, An RTL Methodology to Enable Low Overhead Combinational Testing, Proceedings of the 1997 European conference on Design and Test, p.146, March 17-20, 1997
	Xinli Gu , Erik Larsson , Krzysztof Kuchinski , Zebo Peng, A Controller Testability Analysis and Enhancement Technique, Proceedings of the 1997 European conference on Design and Test, p.153, March 17-20, 1997
	M. L. Flottes , R. Pires , B. Rouzeyre, Analyzing Testability from Behavioral to RT Level, Proceedings of the 1997 European conference on Design and Test, p.158, March 17-20, 1997
	Victor Fernandez , Pablo Sanchez, Partial Scan High-Level Synthesis, Proceedings of the 1996 European conference on Design and Test, p.481, March 11-14, 1996
	Sandhya Seshadri , Michael S. Hsiao, Behavioral-Level DFT via Formal Operator Testability Measures, Journal of Electronic Testing: Theory and Applications, v.18 n.6, p.595-611, December 2002