A layout estimation algorithm for RTL datapaths

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A layout estimation algorithm for RTL datapaths

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 285 - 291

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

Mehrdad Nourani
Christos Papachristou

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 9, Downloads (12 Months): 19, Citation Count: 7

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	A. Wu, V. Chaiyakul and D. Gajski "Layout-Area Models for High-Level Synthesis," in Proc. ICCAD Conj., 1991.
	2	Jen-Pin Weng , Alice C. Parker, 3D scheduling: high-level synthesis with floorplanning, Proceedings of the 28th conference on ACM/IEEE design automation, p.668-673, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127748]
	3	F. Kurdahi and A. Parker, "Techniques for Area Estimation of VLSI Layouts," in IEEE Trans. on CAD, Jan. 1989.
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	12	Fadi J. Kurdahi , Champaka Ramachandran, LAST: a Layout Area and Shape function esTimator for high level applications, Proceedings of the conference on European design automation, February 25-28, 1991, Amsterdam, The Netherlands
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	15	B. Green and L. Turner, "New Limit Cycle Bounds for Digital Filters," IEEE Trans. Circuits and Systems, April 1988.
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	17	S. Y. Kung , Thomas Kailath , Harper J. Whitehouse, VLSI and Modern Signal Processing, Prentice Hall Professional Technical Reference, 1984

CITED BY 7

	M. Knieser , C. Papachristou, COMET: a hardware-software codesign methodology, Proceedings of the conference on European design automation, p.178-183, September 1996, Geneva, Switzerland
	Donald S. Gelosh , Dorothy E. Setliff, Deriving efficient area and delay estimates by modeling layout tools, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.402-407, June 12-16, 1995, San Francisco, California, United States
	Donald S. Gelosh , Dorothy E. Steliff, Modeling layout tools to derive forward estimates of area and delay at the RTL level, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.3, p.451-491, July 2000
	C. Papachristou , M. Nourani, False path exclusion in delay analysis of RTL-based datapath-controller designs, Proceedings of the conference on European design automation, p.336-341, September 1996, Geneva, Switzerland
	Mehrdad Nourani , Christos A. Papachristou, False path exclusion in delay analysis of RTL structures, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.1, p.30-43, 2/1/2002
	Christos Papachristou , Haidar Harmanani , Mehrdad Nourani, An approach for redesigning in data path synthesis, Proceedings of the 30th international conference on Design automation, p.419-423, June 14-18, 1993, Dallas, Texas, United States
	Shen Zhaoxuan , Jong Ching Chuen, Lower bound estimation of hardware resources for scheduling in high-level synthesis, Journal of Computer Science and Technology, v.17 n.6, p.718-730, November 2002