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On computing the transitive closure of a state transition relation
Full text PdfPdf (514 KB)
Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents
Dallas, Texas, United States
Pages: 260 - 265  
Year of Publication: 1993
ISBN:0-89791-577-1
Authors
Yusuke Matsunaga
Patrick C. McGeer
Robert K. Brayton
Sponsors
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 12,   Downloads (12 Months): 29,   Citation Count: 10
Additional Information:

references   cited by   index terms   collaborative colleagues  

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DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/157485.164884
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Alfred V. Aho , John E. Hopcroft, The Design and Analysis of Computer Algorithms, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1974
2
Karl S. Brace , Richard L. Rudell , Randal E. Bryant, Efficient implementation of a BDD package, Proceedings of the 27th ACM/IEEE conference on Design automation, p.40-45, June 24-27, 1990, Orlando, Florida, United States  [doi>10.1145/123186.123222]
 
3
Randal E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Transactions on Computers, v.35 n.8, p.677-691, Aug. 1986  [doi>10.1109/TC.1986.1676819]
4
J. R. Burch , E. M. Clarke , K. L. McMillan , David L. Dill, Sequential circuit verification using symbolic model checking, Proceedings of the 27th ACM/IEEE conference on Design automation, p.46-51, June 24-27, 1990, Orlando, Florida, United States  [doi>10.1145/123186.123223]
 
5
J. R. Burch, E. M. Clarke, K. L. McMillan, D. L. Dill, and J. Hwang. Symbolic model checking: 1020 states and beyond. In Proceedings of the International Symposium on Logic in Computer Science, 1990.
 
6
O. Coudert , C. Berthet , J. C. Madre, Verification of synchronous sequential machines based on symbolic execution, Proceedings of the international workshop on Automatic verification methods for finite state systems, p.365-373, February 1990, Grenoble, France
 
7
O. Coudert and J. C. Madre. A unified framework for the formal verification of sequential circuits. In IEEE International Conference on Computer-Aided Design, 1990.
 
8
K. Karplus. Representing boolean functions with ifthen-else DAGs. In Decennial CalTech VLSI Conference, 1989.

CITED BY  10
Gary D. Hachtel , Enrico Macii , Abelardo Pardo , Fabio Somenzi, Probabilistic analysis of large finite state machines, Proceedings of the 31st annual conference on Design automation, p.270-275, June 06-10, 1994, San Diego, California, United States
Aiguo Xie , Peter A. Beerel, Efficient state classification of finite state Markov chains, Proceedings of the 35th annual conference on Design automation, p.605-610, June 15-19, 1998, San Francisco, California, United States
Radu Marculescu , Diana Marculescu , Massoud Pedram, Non-stationary effects in trace-driven power analysis, Proceedings of the 1999 international symposium on Low power electronics and design, p.133-138, August 16-17, 1999, San Diego, California, United States
M. Fujita , P. C. McGeer , J. C.-Y. Yang, Multi-Terminal Binary Decision Diagrams: An Efficient DataStructure for Matrix Representation, Formal Methods in System Design, v.10 n.2-3, p.149-169, April -May 1997
Enric Pastor , Jordi Cortadella , Oriol Roig, Symbolic Analysis of Bounded Petri Nets, IEEE Transactions on Computers, v.50 n.5, p.432-448, May 2001
Andrew S. Miner, Implicit GSPN reachability set generation using decision diagrams, Performance Evaluation, v.56 n.1-4, p.145-165, March 2004
Ralf Wimmer , Marc Herbstritt , Bernd Becker, Optimization techniques for BDD-based bisimulation computation, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy
Gianpiero Cabodi , Paolo Camurati , Claudio Passerone , Stefano Quer, Computing timed transition relations for sequential cycle-based simulation, Proceedings of the conference on Design, automation and test in Europe, p.4-es, January 1999, Munich, Germany
G. Cabodi , P. Camurati , L. Lavagno , S. Quer, Verification and Synthesis of Counters Based on Symbolic Techniques, Proceedings of the 1997 European conference on Design and Test, p.176, March 17-20, 1997
Quan Hoang Nguyen , Bernhard Scholz, Computing SSA Form with Matrices, Electronic Notes in Theoretical Computer Science (ENTCS), v.190 n.1, p.121-132, July, 2007

INDEX TERMS

Primary Classification:
  F. Theory of Computation
  F.1 COMPUTATION BY ABSTRACT DEVICES
      F.1.1 Models of Computation
          Subjects: Automata (e.g., finite, push-down, resource-bounded)

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.1 Design Styles
          Subjects: Sequential circuits

  F. Theory of Computation
  F.2 ANALYSIS OF ALGORITHMS AND PROBLEM COMPLEXITY
      F.2.1 Numerical Algorithms and Problems
          Subjects: Computations on matrices
      F.2.2 Nonnumerical Algorithms and Problems
          Subjects: Computations on discrete structures

  G. Mathematics of Computing
  G.2 DISCRETE MATHEMATICS


General Terms:
Algorithms, Design, Experimentation, Theory, Verification

Collaborative Colleagues:
Yusuke Matsunaga: colleagues
Patrick C. McGeer: colleagues
Robert K. Brayton: colleagues

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