A cost-based approach to partial scan

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A cost-based approach to partial scan

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 255 - 259

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

Prashant S. Parikh
Miron Abramovici

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 13, Downloads (12 Months): 17, Citation Count: 10

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	E. Trischler, "Testability Analysis and Incomplete Scan Path," ICCAD-83, pp. 38-39, 1983.
	2	K.-T. Cheng , V. D. Agrawal, A Partial Scan Method for Sequential Circuits with Feedback, IEEE Transactions on Computers, v.39 n.4, p.544-548, April 1990 [doi>10.1109/12.54847]
	3	S. Bhawmik, C. J. Lin, K. T. Cheng, and V. D. Agrawal, "PASCANT: A Partial Scan and Test Generation System," Proc. Custom Intesrated Circuits Conf., pp. 17.3.1-17.3.4, May 1991.
	4	D. H. Lee and S. M. Reddy, "On Determining Scan Flip-Flops in Partial-Scan," ICCAD-90, pp. 322-325, Nov. 1990.
	5	H. H. S. Gundlach and K.-D. Muller-Glaser, "On Automatic Testpoint Insertion in Sequential Circuits," Proc. lntn'l. Test Confi, pp. 1072-1079, 1990.
	6	Hyoung B. Min , William A. Rogers, A test methodology for finite state machines using partial scan design, Journal of Electronic Testing: Theory and Applications, v.3 n.2, p.127-137, May 1992 [doi>10.1007/BF00137250]
	7	R. Gupta , M. A. Breuer, The Ballast Methodology for Structured Partial Scan Design, IEEE Transactions on Computers, v.39 n.4, p.538-544, April 1990 [doi>10.1109/12.54846]
	8	A. Kunzmann , J. J. Wunderlich, An analytical approach to the partial scan problem, Journal of Electronic Testing: Theory and Applications, v.1 n.2, p.163-174, May 1990 [doi>10.1007/BF00137392]
	9	Miron Abramovici , James J. Kulikowski , Rabindra K. Roy, The Best Flip-Flops to Scan, Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner, p.166-173, October 26-30, 1991
	10	H.-K. T. Ma, S. Devadas, A. R. Newton, and A. Sangiovanni-Vincentelli, "Test Generation for Sequential Circuits," IEEE Trans. on CAD, pp. 1081-1093, Oct. 1988
	11	Vishiwani D. Agrawal , Kwang-Ting Cheng , Daniel D. Johnson , Tony Sheng Lin, Designing Circuits with Partial Scan, IEEE Design & Test, v.5 n.2, p.8-15, March 1988 [doi>10.1109/54.2032]
	12	V. Chickermane and J. H. Patel, "A Fault Oriented Partial Scan Design Approach," ICCAD-91,, pp. 400-403, Nov. 1991.
	13	Kee S. Kim and C. R. Kime, "Partial Scan by Use of Empirical Testability," ICCAD-90, pp. 314-317, Nov. 1990.
	14	Magdy Abadir , Rohit Kapur , Joe Newman, CHEOPS: cost-driven heuristic for partial scan, Economics of design and test for electronic circuits and systems, Ellis Horwood, Upper Saddle River, NJ, 1992
	15	T. H. Chen and M. A. Breuer, "Automatic Design for Testability Via Testability Measures," IEEE Transactions on CAD, pp. 3-11, January 1985.
	16	Lawrence H. Goldstein , Evelyn L. Thigpen, SCOAP: Sandia controllability/observability analysis program, Proceedings of the 17th conference on Design automation, p.190-196, June 23-25, 1980, Minneapolis, Minnesota, United States [doi>10.1145/800139.804528]
	17	Miron Abramovici , Prashant S. Parikh, Warning: 100% Fault Coverage May Be Misleading!!, Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design, p.662-668, September 20-24, 1992
	18	Wu-Tung Cheng , Tapan J. Chakraborty, Gentest: An Automatic Test-Generation System for Sequential Circuits, Computer, v.22 n.4, p.43-49, April 1989 [doi>10.1109/2.25381]

CITED BY 10

	M.-L. Flottes , C. Landrault , A. Petitqueux, A Unified DFT Approach for BIST and External Test, Journal of Electronic Testing: Theory and Applications, v.19 n.1, p.49-60, February 2003
	M. L. Flottes , R. Pires , B. Rouzeyre , L. Volpe, Scanning datapaths: a fast and effective partial scan selection technique, Proceedings of the conference on Design, automation and test in Europe, p.921-922, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Chau-Shen Chen , Kuang-Hui Lin , TingTing Hwang, Layout driven selecting and chaining of partial scan flip-flops, Proceedings of the 33rd annual conference on Design automation, p.262-267, June 03-07, 1996, Las Vegas, Nevada, United States
	Peichen Pan , C. L. Liu, Partial scan with pre-selected scan signals, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.189-194, June 12-16, 1995, San Francisco, California, United States
	Srimat T. Chakradhar , Arun Balakrishnan , Vishwani D. Agrawal, An exact algorithm for selecting partial scan flip-flops, Proceedings of the 31st annual conference on Design automation, p.81-86, June 06-10, 1994, San Diego, California, United States
	Dong Xiang , Srikanth Venkataraman , W. Kent Fuchs , Janak H. Patel, Partial scan design based on circuit state information, Proceedings of the 33rd annual conference on Design automation, p.807-812, June 03-07, 1996, Las Vegas, Nevada, United States
	Jing-yang Jou , Kwang-ting (tim) Cheng, Timing-Driven Partial Scan, IEEE Design & Test, v.12 n.4, p.52-59, December 1995
	Peichen Pan , C. L. Liu, Partial Scan with Preselected Scan Signals, IEEE Transactions on Computers, v.48 n.9, p.1000-1005, September 1999
	Chau-Shen Chen , Tingting Hwang, Layout Driven Selection and Chaining of Partial Scan Flip-Flops, Journal of Electronic Testing: Theory and Applications, v.13 n.1, p.19-27, Aug. 1, 1998
	Bruce S. Greene , Samiha Mourad, Partial Scan Testing on the Register-Transfer Level, Journal of Electronic Testing: Theory and Applications, v.18 n.6, p.613-626, December 2002