Partial scan with retiming

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Partial scan with retiming

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 249 - 254

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

Dimitrios Kagaris
Spyros Tragoudas

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 10, Downloads (12 Months): 12, Citation Count: 8

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	M. Abramovici, M. A. Breuer, A. D. Friedman, Digital Systems Testing and Testable Design, Computer Science Pres~, New York, 1990.
	2	K.-T. Cheng , V. D. Agrawal, A Partial Scan Method for Sequential Circuits with Feedback, IEEE Transactions on Computers, v.39 n.4, p.544-548, April 1990 [doi>10.1109/12.54847]
	3	V. Chickermane, J. H. Patel, "An Optimization Based App:roach to the Partial Scan Problem", IEEE Int. Test Conf., pp 377- 386, 1990.
	4	V. Chickermane, J. H. Patel, "A Fault Oriented Partiali Scan Approach", IEEE ICCAD'91, pp. 400-403, Nov. 1991.
	5	Thomas T. Cormen , Charles E. Leiserson , Ronald L. Rivest, Introduction to algorithms, MIT Press, Cambridge, MA, 1990
	6	John P. Fishburn, A depth-decreasing heuristic for combinational logic: or how to convert a ripple-carry adder into a carry-lookahead adder or anything in-between, Proceedings of the 27th ACM/IEEE conference on Design automation, p.361-364, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123305]
	7	Michael R. Garey , David S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, W. H. Freeman & Co., New York, NY, 1979
	8	R. Gupta , M. A. Breuer, The Ballast Methodology for Structured Partial Scan Design, IEEE Transactions on Computers, v.39 n.4, p.538-544, April 1990 [doi>10.1109/12.54846]
	9	J.-Y. Jou, K.-T. Cheng, "Timing-Driven Partial Scan", 1EEE 1CCAD'91, pp. 404-407, Nov. 1991.
	10	D. Kagaris, S.Tragoudas, "Partial Scan with Retiming", Technical Report, CS Dept., Southern Illinois University, March 1993.
	11	A. Kunzmann , J. J. Wunderlich, An analytical approach to the partial scan problem, Journal of Electronic Testing: Theory and Applications, v.1 n.2, p.163-174, May 1990 [doi>10.1007/BF00137392]
	12	D. H. Lee, S. M. R~ddy, "On Determining Scan Flip-Flops in Partial-Scan Designs" IEEE ICCA D'90, pp. 322-325, Nov. 1990.
	13	C. E. Leiserson, J. B. Saxe, "Retiming Synchronous Circuitry", Algorithrniea~ Vol. 6, pp. 5-35, 1991.
	14	Thomas Niermann , Janak H. Patel, HITEC: a test generation package for sequential circuits, Proceedings of the conference on European design automation, February 25-28, 1991, Amsterdam, The Netherlands
	15	Texas Instruments Eng. Staff, The TTL Data Book for Design Engineers, 2nd ed., Texas Instruments Inc., Dallas TX, 1976.
	16	H.-J. Wunderlich, S. Hellebrand, "The Pseudoexhaustive Test of Sequential Circuits," IEEE Trans. on Computer-Aided Design, vol. CAD-I1, pp. 26-32, Jan. 1992.

CITED BY 8

	Chau-Shen Chen , Kuang-Hui Lin , TingTing Hwang, Layout driven selecting and chaining of partial scan flip-flops, Proceedings of the 33rd annual conference on Design automation, p.262-267, June 03-07, 1996, Las Vegas, Nevada, United States
	Srimat T. Chakradhar , Sujit Dey, Resynthesis and retiming for optimum partial scan, Proceedings of the 31st annual conference on Design automation, p.87-93, June 06-10, 1994, San Diego, California, United States
	Peichen Pan , C. L. Liu, Partial scan with pre-selected scan signals, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.189-194, June 12-16, 1995, San Francisco, California, United States
	Huoy-Yu Liou , Ting-Ting Y. Lin, Area efficient pipelined pseudo-exhaustive testing with retiming, Proceedings of the 33rd annual conference on Design automation, p.274-279, June 03-07, 1996, Las Vegas, Nevada, United States
	Hideo Fujiwara, A New Class of Sequential Circuits with Combinational Test Generation Complexity, IEEE Transactions on Computers, v.49 n.9, p.895-905, September 2000
	Peichen Pan , C. L. Liu, Partial Scan with Preselected Scan Signals, IEEE Transactions on Computers, v.48 n.9, p.1000-1005, September 1999
	Chau-Shen Chen , Tingting Hwang, Layout Driven Selection and Chaining of Partial Scan Flip-Flops, Journal of Electronic Testing: Theory and Applications, v.13 n.1, p.19-27, Aug. 1, 1998
	Hiroyuki Yotsuyanagi , Seiji Kajihara , Kozo Kinoshita, Synthesis of Sequential Circuits by Redundancy Removal and Retiming, Journal of Electronic Testing: Theory and Applications, v.11 n.1, p.81-92, Aug. 1997