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Sequential circuit test generation on a distributed system
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents
Dallas, Texas, United States
Pages: 107 - 111  
Year of Publication: 1993
ISBN:0-89791-577-1
Authors
Sponsors
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 5,   Downloads (12 Months): 8,   Citation Count: 5
Additional Information:

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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T.M. Niermann, W.-T. Cheng, and J.H. Patel, "PROOFS: A Fast, Memory-Efficient Sequential Circuit Fault Simulator," IEEE Trans. CAD, Vol. 11, pp. 198-207, February 1992.
 
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B. Bencivenga, T.J. Chakraborty, and S. Davidson, "The Architecture of the GenTest Sequential Circuit Test Generator," Proc. Custom Integrated Circuits Conference, pp. 17.1.1-17.1.4, May 1991.
 
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Collaborative Colleagues:
P. Agrawal: colleagues
V. D. Agrawal: colleagues
J. Villoldo: colleagues