Sequential synthesis for table look up programmable gate arrays

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Sequential synthesis for table look up programmable gate arrays

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 224 - 229

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

Rajeev Murgai
Robert K. Brayton
Albert Sangiovanni-Vincentelli

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 8, Downloads (12 Months): 15, Citation Count: 5

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Xilinx Inc., 2069, Hamilton Ave. San Jose, CA-95125, The Programmable Gate Array Data Book, 1990.
	2	Rajeev Murgai , Yoshihito Nishizaki , Narendra Shenoy , Robert K. Brayton , Alberto Sangiovanni-Vincentelli, Logic synthesis for programmable gate arrays, Proceedings of the 27th ACM/IEEE conference on Design automation, p.620-625, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123421]
	3	Kevin Karplus, Xmap: A technology mapper for table-lookup field-programmable gate arrays, Proceedings of the 28th conference on ACM/IEEE design automation, p.240-243, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127672]
	4	Robert Francis , Jonathan Rose , Zvonko Vranesic, Chortle-crf: Fast technology mapping for lookup table-based FPGAs, Proceedings of the 28th conference on ACM/IEEE design automation, p.227-233, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127670]
	5	R. Murgai, N. Shenoy, R. K. Brayton and A. Sangiovanni-Vincentelli, "Improved Logic Synthesis Algorithms for Table Look Up Architectures", Prec. ICCAD, Nov. 1991.
	6	H. -J. Mathony,"Universal logic design algorithm and its application to the synthesis of two-level switching circuits", lEE Proc., Vol. 136, Pt. E, No. 3, May 1989.
	7	J.P. Roth and R.M. Karp, "Minimization overBoolean graphs",iBMJ, of Research and Development, April 1962.
	8	R.K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. R. Wang, "MIS: A Multiple-LevelLogic Optimization System", IEEE Transactions on CAD, November 1987.
	9	R.L. Rudell, "Logic Synthesis forVLSI Design", UCB/ERLMemorandumM89/49, April 1989.
	10	Ellen Sentovich , Kanwar Jit Singh , Cho W. Moon , Hamid Savoj , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Sequential Circuit Design Using Synthesis and Optimization, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.328-333, October 11-14, 1992
	11	B. Lin, and A. R. Newton, "Synthesis of multiple level logic from symbolic highlevel description languages", Prec. of the International Conference on VLSI, Munich, 1989.
	12	M. Schlag, P. K. Chan, and J. Kong, "Empirlcal Evaluation of Multilevel Logic Minimization Tools for an FPGA Technology", Oxford 1991 International Workshop on Field Programmable Logic and Applications.
	13	R. Murgai, R. K. Brayton and A. Sangiovanni-Vincentelli,"Sequential Synthesis for Table Look Up Programmable Gate Arrays", Internal Report, Univ. of California, Berkeley.

CITED BY 5

	Jason Cong , Yuzheng Ding, Combinational logic synthesis for LUT based field programmable gate arrays, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.2, p.145-204, April 1996
	Peichen Pan , Chih-Chang Lin, A new retiming-based technology mapping algorithm for LUT-based FPGAs, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.35-42, February 22-25, 1998, Monterey, California, United States
	Peichen Pan , C. L. Liu, Optimal clock period FPGA technology mapping for sequential circuits, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.3 n.3, p.437-462, July 1998
	Peichen Pan , C. L. Liu, Technology mapping of sequential circuits for LUT-based FPGAs for performance, Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays, p.58-64, February 11-13, 1996, Monterey, California, United States
	Peichen Pan , C. L. Liu, Optimal clock period FPGA technology mapping for sequential circuits, Proceedings of the 33rd annual conference on Design automation, p.720-725, June 03-07, 1996, Las Vegas, Nevada, United States