On area/depth trade-off in LUT-based FPGA technology mapping

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On area/depth trade-off in LUT-based FPGA technology mapping

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 213 - 218

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

Jason Cong
Yuzheng Ding

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 8, Downloads (12 Months): 23, Citation Count: 19

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Bhat, N. and D. Hill, "Routable Technology Mapping for Ft~As," First Int'l ACM/SIGDA Workshop on Field Programmable Gate Arrays, pp. 143-148, Feb. 1992.
	2	Kuang-Chien Chen , Jason Cong , Yuzheng Ding , Andrew B. Kahng , Peter Trajmar, DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization, IEEE Design & Test, v.9 n.3, p.7-20, July 1992 [doi>10.1109/54.156154]
	3	Jason Cong , Yuzheng Ding, An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.48-53, November 1992, Santa Clara, California, United States
	4	Cong, J. and Y. Ding, "On Area/Depth Trade-off in LUT-Based Ft~A Technology Mapping," UCLA Computer Science Department Tech. Report CSD- 920053, October 1992.
	5	Cong, J., Y. Ding, T. Gao, and K. Chen, "An Optimal Performance-Driven Technology Mapping Algorithm for LUT based FPGAs under Arbitrary Net-Delay Models," Proc. 1993 Int'l Conf. on Computer Graphics and CAD, August 1991.
	6	Robert Francis , Jonathan Rose , Zvonko Vranesic, Chortle-crf: Fast technology mapping for lookup table-based FPGAs, Proceedings of the 28th conference on ACM/IEEE design automation, p.227-233, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127670]
	7	Francis, R. J., J. Rose, and Z. Vranesic, "Technology Mapping for Delay Optimization of Lookup Table- Based FPGAs," MCNC Logic Synthesis Workshop, 1991.
	8	Dwight D. Hill, A CAD system for the design of field programmable gate arrays, Proceedings of the 28th conference on ACM/IEEE design automation, p.187-192, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127662]
	9	Kevin Karplus, Xmap: A technology mapper for table-lookup field-programmable gate arrays, Proceedings of the 28th conference on ACM/IEEE design automation, p.240-243, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127672]
	10	Rajeev Murgai , Yoshihito Nishizaki , Narendra Shenoy , Robert K. Brayton , Alberto Sangiovanni-Vincentelli, Logic synthesis for programmable gate arrays, Proceedings of the 27th ACM/IEEE conference on Design automation, p.620-625, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123421]
	11	Murgai, R., N. Shenoy, R. K. Brayton, and A. Sangiovanni-Vincentelli, "Performance Directed Synthesis for Table Look Up Programmable Gate Arrays," Proc. Int'l Conf. Computer-Aided Design, pp. 572- 575, Nov., 1991.
	12	Murgai, R., N. Shenoy, R. K. Brayton, and A. Sangiovanni-Vincentelli, "Improved Logic Synthesis Algorithms for Table Look Up Architectures ," Proc. int'l Conf. Computer-Aided Design, pp. 564-567, Nov., 1991.
	13	Sawkar, P. and D. Thomas, "Technology Mapping for Table-Look-Up Based Field Programmable Gate Arrays," ACM/SIGDA Workshop on Field Programmable Gate Arrays, pp. 83-88, Feb. 1992.
	14	Martine D. F. Schlag , Jackson Kong , Pak K. Chan, Routability-Driven Techology Mapping for LookUp-Table-Based FPGAs, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.86-90, October 11-14, 1992
	15	Nam-Sung Woo, A heuristic method for FPGA technology mapping based on the edge visibility, Proceedings of the 28th conference on ACM/IEEE design automation, p.248-251, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127675]
	16	Xilinx, The Programmable Gate Array Data Book, Xilinx, San Jose (1992).

CITED BY 19

	Amit Chowdhary , John P. Hayes, Technology mapping for field-programmable gate arrays using integer programming, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.346-352, November 05-09, 1995, San Jose, California, United States
	Jason Cong , Yuzheng Ding, Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.110-114, November 07-11, 1993, Santa Clara, California, United States
	Jason Cong , Yuzheng Ding, Combinational logic synthesis for LUT based field programmable gate arrays, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.2, p.145-204, April 1996
	Christian Legl , Bernd Wurth , Klaus Eckl, A Boolean approach to performance-directed technology mapping for LUT-based FPGA designs, Proceedings of the 33rd annual conference on Design automation, p.730-733, June 03-07, 1996, Las Vegas, Nevada, United States
	Jason Cong , Sung Kyu Lim, Edge separability based circuit clustering with application to circuit partitioning, Proceedings of the 2000 conference on Asia South Pacific design automation, p.429-434, January 2000, Yokohama, Japan
	Amit Singh , Malgorzata Marek-Sadowska, Circuit clustering using graph coloring, Proceedings of the 1999 international symposium on Physical design, p.164-169, April 12-14, 1999, Monterey, California, United States
	Rajive Bagrodia , Zheng Li , Vikas Jha , Yuan Chen , Jason Cong, Parallel logic level simulation of VLSI circuits, Proceedings of the 26th conference on Winter simulation, p.1354-1361, December 11-14, 1994, Orlando, Florida, United States
	Jason Cong , Songjie Xu, Technology mapping for FPGAs with embedded memory blocks, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.179-188, February 22-25, 1998, Monterey, California, United States
	Chau-Shen Chen , TingTing Hwang , C. L. Liu, Low power FPGA design—a re-engineering approach, Proceedings of the 34th annual conference on Design automation, p.656-661, June 09-13, 1997, Anaheim, California, United States
	Kalapi Roy-Neogi , Carl Sechen, Multiple FPGA partitioning with performance optimization, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.146-152, February 12-14, 1995, Monterey, California, United States
	Rajive Bagrodia , Yu-an Chen , Vikas Jha , Nicki Sonpar, Parallel gate-level circuit simulation on shared memory architectures, ACM SIGSIM Simulation Digest, v.25 n.1, p.170-174, July 1995
	Jason Cong , Honching Peter Li , Sung Kyu Lim , Toshiyuki Shibuya , Dongmin Xu, Large scale circuit partitioning with loose/stable net removal and signal flow based clustering, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.441-446, November 09-13, 1997, San Jose, California, United States
	Jason Cong , Zheng Li , Rajive Bagrodia, Acyclic multi-way partitioning of Boolean networks, Proceedings of the 31st annual conference on Design automation, p.670-675, June 06-10, 1994, San Diego, California, United States
	Deming Chen , Jason Cong , Fei Li , Lei He, Low-power technology mapping for FPGA architectures with dual supply voltages, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
	Andrew Ling , Deshanand P. Singh , Stephen D. Brown, FPGA technology mapping: a study of optimality, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Yu Hu , Victor Shih , Rupak Majumdar , Lei He, FPGA area reduction by multi-output function based sequential resynthesis, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California
	Chi-Shong Wang , Chingwei Yeh, Performance-driven technology mapping with MSG partition and selective gate duplication, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.4, p.953-973, October 2006
	Min Xu , Fadi Kurdahi, Area and Timing Estimation for Lookup Table Based FPGAs, Proceedings of the 1996 European conference on Design and Test, p.151, March 11-14, 1996
	Fei Li , Lei He , Kewal K. Saluja, Estimation of Maximum Power-up Current, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.51, January 07-11, 2002