Performance directed technology mapping for look-up table based FPGAs

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Performance directed technology mapping for look-up table based FPGAs

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 208 - 212

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

Prashant Sawkar
Donald Thomas

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 14, Citation Count: 15

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	R. Brayton, et. al, "Multiple-level logic optimization system," ICCAD, 1986.
	2	R.J. Francis, J. Rose, Z. Vranesic, "Technology Mapping for Delay Optimization of Lookup Table-Based FPGAs," International Workshop on Logic Synthesis, 1991.
	3	Jason Cong , Yuzheng Ding, An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.48-53, November 1992, Santa Clara, California, United States
	4	R. Murgai, N. Shenoy, R. K. Brayton, A. Sangiovanni- Vincentelli, "Performance Directed Synthesis for Table Look Up Programmable Gate Arrays," ICCAD, 1991.
	5	P. Sawkar , D. Thomas, Area and delay mapping for table-look-up based field programmable gate arrays, Proceedings of the 29th ACM/IEEE conference on Design automation, p.368-373, June 08-12, 1992, Anaheim, California, United States
	6	Xilinx Programmable Gate Array Data Book, Xilinx Corporation, 1989.
	7	E S. Hauge, R. Nair, and E. J. Yoffa, "Circuit Placement For Predictable Performance," ICCAD 1987.

CITED BY 15

	Jason Cong , Yuzheng Ding, Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.110-114, November 07-11, 1993, Santa Clara, California, United States
	Jason Cong , Yuzheng Ding, Combinational logic synthesis for LUT based field programmable gate arrays, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.2, p.145-204, April 1996
	Sudip K. Nag , Rob A. Rutenbar, Performance-driven simultaneous place and route for row-based FPGAs, Proceedings of the 31st annual conference on Design automation, p.301-307, June 06-10, 1994, San Diego, California, United States
	Peichen Pan , Chih-Chang Lin, A new retiming-based technology mapping algorithm for LUT-based FPGAs, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.35-42, February 22-25, 1998, Monterey, California, United States
	Kalapi Roy-Neogi , Carl Sechen, Multiple FPGA partitioning with performance optimization, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.146-152, February 12-14, 1995, Monterey, California, United States
	Christian Legl , Bernd Wurth , Klaus Eckl, A Boolean approach to performance-directed technology mapping for LUT-based FPGA designs, Proceedings of the 33rd annual conference on Design automation, p.730-733, June 03-07, 1996, Las Vegas, Nevada, United States
	Peichen Pan , C. L. Liu, Optimal clock period FPGA technology mapping for sequential circuits, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.3 n.3, p.437-462, July 1998
	Peichen Pan , C. L. Liu, Technology mapping of sequential circuits for LUT-based FPGAs for performance, Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays, p.58-64, February 11-13, 1996, Monterey, California, United States
	Jason Cong , Yean-Yow Hwang, Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA design, Proceedings of the 33rd annual conference on Design automation, p.726-729, June 03-07, 1996, Las Vegas, Nevada, United States
	Jason Cong , Yean-Yow Hwang, Partially-dependent functional decomposition with applications in FPGA synthesis and mapping, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.35-42, February 09-11, 1997, Monterey, California, United States
	Sudip K. Nag , Rob A. Rutenbar, Performance-driven simultaneous place and route for island-style FPGAs, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.332-338, November 05-09, 1995, San Jose, California, United States
	Jason Cong , Yean-Yow Hwang, Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.2, p.193-225, April 2000
	Juinn-Dar Huang , Jing-Yang Jou , Wen-Zen Shen, An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.13-17, November 10-14, 1996, San Jose, California, United States
	Hao Li , Srinivas Katkoori , Wai-Kei Mak, Power minimization algorithms for LUT-based FPGA technology mapping, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.9 n.1, p.33-51, January 2004
	M. Teslenko , E. Dubrova, Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.748-751, November 07-11, 2004