An efficient method of partitioning circuits for multiple-FPGA implementation.

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An efficient method of partitioning circuits for multiple-FPGA implementation.

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 202 - 207

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

Nam Sung Woo
Jaeseok Kim

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 12, Downloads (12 Months): 24, Citation Count: 17

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	L. A. Sanchis, Multiple-Way Network Partitioning, IEEE Transactions on Computers, v.38 n.1, p.62-81, January 1989 [doi>10.1109/12.8730]
	2	Ching-Wei Yeh , Chung-Kuan Cheng , Ting-Ting Y. Lin, A general purpose multiple way partitioning algorithm, Proceedings of the 28th conference on ACM/IEEE design automation, p.421-426, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127706]
	3	M. Shih , E. S. Kuh , R.-S. Tsay, Performance-driven system partitioning on multi-chip modules, Proceedings of the 29th ACM/IEEE conference on Design automation, p.53-56, June 08-12, 1992, Anaheim, California, United States
	4	Abramovici M., "Fpgasplit," personal communication, OcL 1992.
	5	C. M. Fiduccia , R. M. Mattheyses, A linear-time heuristic for improving network partitions, Proceedings of the 19th conference on Design automation, p.175-181, January 1982
	6	Krisimammlhy B., "An Improved Min-Cut Algorithm for Partitioning VLSI Networks," IEEE Transactions on Computers, Vol. C-33, No. 5, pp. 438-446, 1984.
	7	A. B. Kahng, Fast hypergraph partition, Proceedings of the 26th ACM/IEEE conference on Design automation, p.762-766, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74524]
	8	Donath W., Logic Partitioning, Chapter 9, Preas B. and Lorenzetti M. eds., Physical Design Automation of VLSI Systems, Benjamin Pub., 1988.
	9	Britton B., Hill D., Oswald B., Woo N-S, $ingh $., "~zed Reconfigurable Cell Array Architecture for High- Performance Field Programmable Gate Arrays," Submitted for publication at 1993 Custom Integrated Circuit Conference.
	10	AT&T 3000 Series Field.Programmable gate Arrays, AT&T Microelectronics, 1991.
	11	Xilinx XC4000 FPGA data book, Xilinx inc., 1991.
	12	RPM Emulation System, Quickmm Co.. 1990.
	13	G. Vijayan, Min-cost partitioning on a tree structure and applications, Proceedings of the 26th ACM/IEEE conference on Design automation, p.771-774, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74526]
	14	Woo N-S., Kim I., "MP2: An Efficient Multi-way Partitioning Method with Pin Constraints for Multiple-FleA Implementation," Technical Report, AT&T Bell I.,a~ratories, Oct. 1992.

CITED BY 17

	Maogang Wang , Sung Lim , Jason Cong , Majid Sarrafzadeh, Multi-way partitioning using bi-partition heuristics, Proceedings of the 2000 conference on Asia South Pacific design automation, p.667, January 2000, Yokohama, Japan
	Dennis J.-H. Huang , Andrew B. Kahng, Multi-way system partitioning into a single type or multiple types of FPGAs, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.140-145, February 12-14, 1995, Monterey, California, United States
	Roman Kužnar , Franc Brglez, PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.644-649, November 05-09, 1995, San Jose, California, United States
	Roman Kužnar , Franc Brglez , Baldomir Zajc, Multi-way netlist partitioning into heterogeneous FPGAs and minimization of total device cost and interconnect, Proceedings of the 31st annual conference on Design automation, p.238-243, June 06-10, 1994, San Diego, California, United States
	Kalapi Roy-Neogi , Carl Sechen, Multiple FPGA partitioning with performance optimization, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.146-152, February 12-14, 1995, Monterey, California, United States
	Wen-Jong Fang , Allen C.-H. Wu, Performance-driven multi-FPGA partitioning using functional clustering and replication, Proceedings of the 35th annual conference on Design automation, p.283-286, June 15-19, 1998, San Francisco, California, United States
	Sverre Wichlund, On multilevel circuit partitioning, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.505-511, November 08-12, 1998, San Jose, California, United States
	Roman Kužnar , Baldomir Zajc , Franc Brglez, A unified cost model for min-cut partitioning with replication applied to optimization of large heterogeneous FPGA partitions, Proceedings of the conference on European design automation, p.271-276, September 19-23, 1994, Grenoble, France
	Ranga Vemuri , Sriram Govindarajan , Iyad Ouaiss , Meenakshi Kaul , Vinoo Srinivasan , Shankar Radhakrishnan , Sujatha Sundaraman , Satish Ganesan , Awartika Pandey , Preetham Lakshmikanthan, Automated design synthesis and partitioning for adaptive reconfigurable hardware, Hardware implementation of intelligent systems, Physica-Verlag GmbH, Heidelberg, Germany, 2001
	Wen-Jong Fang , Allen C.-H. Wu, Multi-way FPGA partitioning by fully exploiting design hierarchy, Proceedings of the 34th annual conference on Design automation, p.518-521, June 09-13, 1997, Anaheim, California, United States
	Huiqun Liu , D. F. Wong, Network flow based multi-way partitioning with area and pin constraints, Proceedings of the 1997 international symposium on Physical design, p.12-17, April 14-16, 1997, Napa Valley, California, United States
	Wen-Jong Fang , Allen C.-H. Wu, A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.638-643, November 10-14, 1996, San Jose, California, United States
	Pak K. Chan , Martine D. F. Schlag , Jason Y. Zien, Spectral-based multi-way FPGA partitioning, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.133-139, February 12-14, 1995, Monterey, California, United States
	Nan-Chi Chou , Lung-Tien Liu , Chung-Kuan Cheng , Wei-Jin Dai , Rodney Lindelof, Circuit partitioning for huge logic emulation systems, Proceedings of the 31st annual conference on Design automation, p.244-249, June 06-10, 1994, San Diego, California, United States
	Wen-Jong Fang , Allen C.-H. Wu, Multiway FPGA partitioning by fully exploiting design hierarchy, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.1, p.34-50, Jan. 2000
	Shantanu Dutt , Halim Theny, Partitioning around roadblocks: tackling constraints with intermediate relaxations, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.350-355, November 09-13, 1997, San Jose, California, United States
	Masato Inagi , Yasuhiro Takashima , Yuichi Nakamura , Yoji Kajitani, A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, v.E90-A n.5, p.924-931, May 2007