Reliable non-zero skew clock trees using wire width optimization

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Reliable non-zero skew clock trees using wire width optimization

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 165 - 170

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

Satyamurthy Pullela
Noel Menezes
Lawrence T. Pillage

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 9, Downloads (12 Months): 24, Citation Count: 25

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Curtis L. Ratzlaff , Nanda Gopal , Lawrence T. Pillage, RICE: Rapid interconnect circuit evaluator, Proceedings of the 28th conference on ACM/IEEE design automation, p.555-560, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127732]
	2	W. C. Elmore. "The transient response of damped linear networks with particular regard to wideband amplifiers," J. Applied Physics, 19(1), 1948.
	3	L. T. Pillage and R. A. Rohrer. Asymptotic waveform evaluation for timing analysis. IEEE Trans. Comp. Aided Design, 9, 1990.
	4	Ren-Song Tsay. "Exact zero skew," Proc. IEEE Int'l. Conf. Computer.Aided Des., Nov. 1991.
	5	Michael A. B. Jackson , Arvind Srinivasan , E. S. Kuh, Clock routing for high-performance ICs, Proceedings of the 27th ACM/IEEE conference on Design automation, p.573-579, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123406]
	6	T.-H. Chao , J.-M. Ho , Y.-C. Hsu, Zero skew clock net routing, Proceedings of the 29th ACM/IEEE conference on Design automation, p.518-523, June 08-12, 1992, Anaheim, California, United States
	7	Paul Penfield, Jr. , Jorge Rubinstein, Signal delay in RC tree networks, Proceedings of the 18th conference on Design automation, p.613-617, June 29-July 01, 1981, Nashville, Tennessee, United States
	8	Andrew Kahng , Jason Cong , Gabriel Robins, High-performance clock routing based on recursive geometric matching, Proceedings of the 28th conference on ACM/IEEE design automation, p.322-327, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127688]
	9	S. W. Director and K. A. ttohrer. "The generalized adjoint network sensitivities," IEEE Trans. Circuit Theory, Vol. CT-16, no. 3, Aug. 1969.
	10	C. J. Terman. "Simulation tools for digital LSI design," PhD thesis, Massachusetts Institute of Technology, Sept. 1983.
	11	C. L. Ratzlaff, S. Pullela, and L. T. Pillage. "Modeling the RC-interconnect effects in a hierarchical timing analyzer," Proc. IEEE Custom Integrated Circuits Conf., 1992

CITED BY 25

	Ying Liu , Sani R. Nassif , Lawrence T. Pileggi , Andrzej J. Strojwas, Impact of interconnect variations on the clock skew of a gigahertz microprocessor, Proceedings of the 37th conference on Design automation, p.168-171, June 05-09, 2000, Los Angeles, California, United States
	Gary Ellis , Lawrence T. Pileggi , Rob A. Rutenbar, A hierarchical decomposition methodology for multistage clock circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.266-273, November 09-13, 1997, San Jose, California, United States
	Joe G. Xi , Wayne W. M. Dai, Buffer insertion and sizing under process variations for low power clock distribution, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.491-496, June 12-16, 1995, San Francisco, California, United States
	Rony Kay , Gennady Bucheuv , Lawrence T. Pileggi, EWA: exact wiring-sizing algorithm, Proceedings of the 1997 international symposium on Physical design, p.178-185, April 14-16, 1997, Napa Valley, California, United States
	Chung-Ping Chen , Yao-Wen Chang , D. F. Wong, Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation, Proceedings of the 33rd annual conference on Design automation, p.405-408, June 03-07, 1996, Las Vegas, Nevada, United States
	Shantanu Ganguly , Daksh Lehther , Satyamurthy Pullela, Clock Distribution Methodology for PowerPC™Microprocessors, Journal of VLSI Signal Processing Systems, v.16 n.2-3, p.181-189, June/July 1997
	Ashok Vittal , Malgorzata Marek-Sadowska, Power optimal buffered clock tree design, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.497-502, June 12-16, 1995, San Francisco, California, United States
	I-Min Liu , Tan-Li Chou , Adnan Aziz , D. F. Wong, Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion, Proceedings of the 2000 international symposium on Physical design, p.33-38, May 2000, San Diego, California, United States
	Yu-Min Lee , Hing Yin Lai , Charlie Chung-Ping Chen, Optimal spacing and capacitance padding for general clock structures, Proceedings of the 2001 conference on Asia South Pacific design automation, p.115-119, January 2001, Yokohama, Japan
	M. Seki , K. Kato , S. Kobayashi , K. Tsurusaki, A practical clock router that accounts for the capacitance derived from parallel and cross segments, Proceedings of the conference on European design automation, p.362-367, September 1996, Geneva, Switzerland
	Noel Menezes , Satyamurthy Pullela , Florentin Dartu , Lawrence T. Pillage, RC interconnect synthesis—a moment fitting approach, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.418-425, November 06-10, 1994, San Jose, California, United States
	Mitsuho Seki , Kenji Inoue , Kazuo Kato , Kouki Tsurusaki , Shin'ichi Fukasawa , Hitoshi Sasaki , Mutsuhito Aizawa, A specified delay accomplishing clock router using multiple layers, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.289-292, November 06-10, 1994, San Jose, California, United States
	Iris Hui-Ru Jiang , Song-Ra Pan , Yao-Wen Chang , Jing-Yang Jou, Optimal reliable crosstalk-driven interconnect optimization, Proceedings of the 2000 international symposium on Physical design, p.128-133, May 2000, San Diego, California, United States
	Dennis J. H. Huang , Andrew B. Kahng , Chung-Wen Albert Tsao, On the bounded-skew clock and Steiner routing problems, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.508-513, June 12-16, 1995, San Francisco, California, United States
	Shantanu Ganguly , Shervin Hojat, Clock distribution design and verification for PowerPC microprocessors, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.58-61, November 05-09, 1995, San Jose, California, United States
	Haihua Su , Sachin S. Sapatnekar, Hybrid structured clock network construction, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Hong-Yean Hsieh , Wentai Liu , Paul Franzon , Ralph Cavin, III, Clocking Optimization and Distribution in Digital Systemswith Scheduled Skews, Journal of VLSI Signal Processing Systems, v.16 n.2-3, p.131-147, June/July 1997
	Anand Rajaram , Jiang Hu , Rabi Mahapatra, Reducing clock skew variability via cross links, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Kai Wang , Malgorzata Marek-Sadowska, Clock network sizing via sequential linear programming with time-domain analysis, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA
	Massoud Pedram , Hirendu Vaishnav, Power Optimization in VLSI Layout: A Survey, Journal of VLSI Signal Processing Systems, v.15 n.3, p.221-232, March 1997
	Anand Rajaram , David Z. Pan , Jiang Hu, Improved algorithms for link-based non-tree clock networks for skew variability reduction, Proceedings of the 2005 international symposium on Physical design, April 03-06, 2005, San Francisco, California, USA
	Uday Padmanabhan , Janet M. Wang , Jiang Hu, Statistical clock tree routing for robustness to process variations, Proceedings of the 2006 international symposium on Physical design, April 09-12, 2006, San Jose, California, USA
	Matthew R. Guthaus , Dennis Sylvester , Richard B. Brown, Clock buffer and wire sizing using sequential programming, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	W.-C. D. Lam , J. Jam , C.-K. Koh , V. Balakrishnan , Y. Chen, Statistical based link insertion for robust clock network design, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.588-591, November 06-10, 2005, San Jose, CA
	Matthew R. Guthaus , Dennis Sylvester , Richard B. Brown, Clock tree synthesis with data-path sensitivity matching, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea