Timing optimization by gate resizing and critical path identification

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Timing optimization by gate resizing and critical path identification

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 135 - 140

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

Wen-Ben Jone
Chen-Liang Fang

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 13, Downloads (12 Months): 30, Citation Count: 3

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	BART86	K. Bartlett, W. Cohen, A. de Geus, and G. Hachtel, "Synthesis and optimization of multi-level logic under timing constarints," IEEE Tear, s. on Computer-Aided Design, vol.5, pp. 582-595, Oct. 1986.
	BURS85	Michael Burstein , Mary N. Youssef, Timing influenced layout design, Proceedings of the 22nd ACM/IEEE conference on Design automation, p.124-130, June 1985, Las Vegas, Nevada, United States [doi>10.1145/317825.317845]
	CHEN90	Kuang-Chien Chen , Saburo Muroga, Timing optimization for multi-level combinational networks, Proceedings of the 27th ACM/IEEE conference on Design automation, p.339-344, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.105253]
	DU89	D. H. Du , S. H. Yen , S. Ghanta, On the general false path problem in timing analysis, Proceedings of the 26th ACM/IEEE conference on Design automation, p.555-560, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74475]
	Fang92	C. L. Fang, "Critical path identification and timing optlmization for circuit synthesis," MS Thsis, Department of Computer Science, New Mexico Tech, Socorro, NM 87801, August 1992.
	GOEL81	P. Goel, "An implicit enumeration algorithm to generate tests for combinational logic circuits," 1EEE Trans, on Computers, vol. c-30, pp. 215-222, March 1981.
	HITC82	R. B. Hitchcock. G. L. Smith, and D. D. Cheng, "Timing analysis of computer hardware," IBM J. Res. Develop., vol. 26, no. 1, pp. 100-105, ,Jan. 1982.
	MARP87	D.Marplc, and A. E1 Gamal, "Optimal selection of transistor size in digital VLSI circuits," Advances in Research in VLSI, MA : MIT Press, 1987.
	MCG91	Patrick C. McGeer , Robert K. Brayton, Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications, Kluwer Academic Publishers, Norwell, MA, 1991
	MICH87	G. De Michell, "Performance-oriented synthesis of largescale domino CMOS circuits," IEEE Trans. on Compuger- Aided Design, vol. CAD-6, pp. 751-764, 1987.

CITED BY 3

	S. C. Prasad , K. Roy, Transistor reordering for power minimization under delay constraint, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.2, p.280-300, April 1996
	How-Rern Lin , TingTing Hwang, Dynamical identification of critical paths for iterative gate sizing, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.481-484, November 06-10, 1994, San Jose, California, United States
	Raul San Martin , John P. Knight, Power-profiler: optimizing ASICs power consumption at the behavioral level, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.42-47, June 12-16, 1995, San Francisco, California, United States