Circuit delay models and their exact computation using Timed Boolean Functions

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Circuit delay models and their exact computation using Timed Boolean Functions

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 128 - 134

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

William K. C. Lam
Robert K. Brayton
Alberto L. Sangiovanni-Vincentelli

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 14, Downloads (12 Months): 35, Citation Count: 8

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	H.C. Chen and D. H. Du. Path sensitization in critical path problem. 1990 ACM Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 1990.
	2	S. Devadas , K. Keutzer , S. Malik , A. Wang, Certified timing verification and the transition delay of a logic circuit, Proceedings of the 29th ACM/IEEE conference on Design automation, p.549-555, June 08-12, 1992, Anaheim, California, United States
	3	S. Devadas, K. Keutzer, and S. Malik. Delay computation in combinational logic circuits: Theory and algorithms. IEEE/ACM International Conference on Computer-AidedDesign, Nov. 1991.
	4	W. Lain, R. Brayton, and A. Sangiovanni-Vincentelli. Circuit delay models and their exact computation using timed boolean functions. UC Berkeley ERL memorandum: UCB/ERL M93/6, Jan. 1993.
	5	W. Lam, R. Brayton, and A. Sangiovanni-Vincentelli. Minimum cycle time of synchronous circuit with bounded delays. UC Berkeley ERL memorandum: UCB/ERL M92/56, May 1992.
	6	William K. C. Lam , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Valid clocking in wavepipelined circuits, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.518-525, November 1992, Santa Clara, California, United States
	7	Patrick C. McGeer , Robert K. Brayton, Provably correct critical paths, Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI, p.119-142, June 1989, Cambridge, Massachusetts, United States
	8	P. McGeer, A. Saldanha, P. Stephan, R. Brayton, and A. Sangiovanni-Vince ntelli. Timing analysis and delay-fault test generation using path recursive functions. IEEE International Conference on Computer-Aided Design, pages 180-183, Nov. 1991.

CITED BY 8

	William K. C. Lam , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Exact minimum cycle times for finite state machines, Proceedings of the 31st annual conference on Design automation, p.100-105, June 06-10, 1994, San Diego, California, United States
	Hakan Yalcin , John P. Hayes, Hierarchical timing analysis using conditional delays, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.371-377, November 05-09, 1995, San Jose, California, United States
	M. Kassab , E. Cerny , S. Aourid , T. Krodel, Propagation of last-transition-time constraints in gate-level timing analysis, Proceedings of the conference on Design, automation and test in Europe, p.796-802, February 23-26, 1998, Le Palais des Congrés de Paris, France
	R. Peset Llopis, Path sensitization of combinational circuits and its impact on clocking of sequential systems, Proceedings of the conference on European design automation, p.210-215, September 18-22, 1995, Brighton, England
	Andreas Jakoby , Rüdiger Reischuk , Christian Schindelhauer, Circuit complexity: from the worst case to the average case, Proceedings of the twenty-sixth annual ACM symposium on Theory of computing, p.58-67, May 23-25, 1994, Montreal, Quebec, Canada
	Jindrich Zejda , Eduard Cerny, Gate-level timing verification using waveform narrowing, Proceedings of the conference on European design automation, p.374-379, September 19-23, 1994, Grenoble, France
	Hakan Yalcin , John P. Hayes, Event propagation conditions in circuit delay computation, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.2 n.3, p.249-280, July 1997
	Suchismita Roy , P. P. Chakrabarti , Pallab Dasgupta, Event propagation for accurate circuit delay calculation using SAT, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.12 n.3, p.1-23, August 2007