A verification technique for gated clock

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A verification technique for gated clock

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 123 - 127

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

Masamichi Kawarabayashi
Narendra Shenoy
Alberto Sangiovanni-Vincentelli

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 11, Downloads (12 Months): 17, Citation Count: 1

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	David E. Wallace , Carlo H. Séquin, ATV: an abstract timing verifier, Proceedings of the 25th ACM/IEEE conference on Design automation, p.154-159, June 12-15, 1988, Atlantic City, New Jersey, United States
	2	N. Weiner , A. Sangiovanni-Vincentelli, Timing analysis in a logic synthesis environment, Proceedings of the 26th ACM/IEEE conference on Design automation, p.655-661, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74498]
	3	Alexander T. Ishii , Charles E. Leiserson, A timing analysis of level-clocked circuitry, Proceedings of the sixth MIT conference on Advanced research in VLSI, p.113-130, March 1990, Boston, Massachusetts, United States
	4	K. Sakallah, T. N. Mudge, and O. A. Olukotun. Timing Verification and Optimal Clocking of Synchronous Digital Circuits. In Proceedings of the International Conference on Computer-Aided Design, pages 552-555. IEEE, 1990.
	5	N. Shenoy, R. K. Brayton, and A. Sangiovanni-Vincentelli. A Pseudo-Polynomial Algorithm for Verification of Clocking Schemes. In Proceedings of the Tan 92:1992 Workshop on Timing Issues in the Specification and Synthesis of Digital System, 1992.
	6	Thomas G. Szymanski , Narendra Shenoy, Verifying clock schedules, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.124-131, November 1992, Santa Clara, California, United States
	7	Michael R. Dagenais , Nicholas C. Rumin, Automatic determination of optimal clocking parameters in synchronous MOS VLSI circuits, Proceedings of the fifth MIT conference on Advanced research in VLSI, p.19-33, January 1988, Cambridge, Massachusetts, United States
	8	Ellen Sentovich , Kanwar Jit Singh , Cho W. Moon , Hamid Savoj , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Sequential Circuit Design Using Synthesis and Optimization, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.328-333, October 11-14, 1992
	9	R. Tsay and I. Lin. A System Timing Verifier for Multi- Phase Level-Sensitive Clock Designs. In IBM Research Report, 1991.
	10	Narendra V. Shenoy , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Retiming of Circuits with Single Phase Transparent Latches, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.86-89, October 14-16, 1991