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 REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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J. P. Roth,"Diagnosis of Automata Failures: A Calculus and a method," IBM J. Res. Develop., vol. 10, pp. 278-291, July 1966.
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P. Goel,"Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits," IEEE Trans. on Comp., vol. C-30, pp. 215-222, Mar. 1981.
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H. Fujiwara, and T. Shimono,"On the Acceleration on Test Generation Algorithms," IEEE Trans. on Comp., vol C-32, pp. 1137-1144, Dec. 1983.
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M. Schulz, E. Trischler, and T. Sarfert,"SOCRATES: A Highly Efficient Automatic Test Pattern Generation System," IEEE Trans. on CAD., pp. 126-137, Jan. 1988.
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M. Schulz, and E. Auth,"Advance~ Automatic Test Pattern Generation and Redundancy Identification Techniques," FTCS-I 8, pp. 30-35, June. 1988.
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J. A. Waicukauski, P. A. Shupe, D. J. Giramma, and A. Matin,"ATPG for Ultra- Large Structured Designs," 1990 ITC, pp. 44-51, Sept. 1990.
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S. B. Akers and W. Jansz, "Test Set Embedding in a Built-In Self-Test Environment," 1989 Intl. Test Conf., pp. 257-263, August 1989.
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H. Higuchi, N. Ishiura, and S. Yajima,"Compaction of Test Sets Based on Symbolic Fault Simulation," Synthesis and Simulation Meeting and International Interchange, pp. 253-262, April 1992.
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P. Goel, and B. C. Rosales,"Test Generation and Dynamic Compaction of Tests," Digest of Papers 1979 Test Conf., pp. 189-192, Oct. 1979.
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L. N. Reddy, I. Pomeranz, and S. M. Reddy,"ROTCO: A Reverse Order Test Compaction Technique," I992 IEEE EURO-ASIC Conference, pp.189-194, Sept. 1992.
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S. B. Akers and B. Krishnamurthy, "On the Application of Test Counting to VLSI Testing," Technical Report No. CR-85-12, Computer Research Laboratory, Tektronix Laboratories, April 1985.
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I. Pomeranz, and S. M. Reddy,"Generalization of Independent Fault Sets for Transition Faults," 1992 IEEE VLSI Test Symposium, pp. 7-12, April 1992, updated version available as Technical Report, Electrical & Computer Eng. Dept, U. of Iowa.
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J. Rajski, and H. Cox,"A Method to Calculate Necessary Assignments in Algorithmic Test Pattem Generation," 1990 ITC, pp. 25-34, Sept. 1990.
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B. Krishnamurthy, and S. B. Akers,"On the Complexity of Estimating the Size of a Test Set," IEEE Trans. on Comp., vol. C-33, pp. 750-753, Aug. 1984.
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17
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Y. Matsunaga, and M. Fujita,"A Fast Test Pattem Generation for Large Scale Circuits," Synthesis and Simulation Meeting and International Interchange, pp. 263- 271, April 1992.
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S. Kajihara, H. Shiba and K. Kinoshita, "Removal of Redundancy in Logic Circuits under Classification of undetectable Faults", Proc. 22nd Fault-Tolerant Computing Symp., July 1992, pp. 263-270.
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F. Brglez, and H. Fujiwara,"A Neutral Netlist of 10 Combinational Benchmark Design and a Special Translator in Fortran," ISCAS'85, June 1985.
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22
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F. Brglez, D. Bryan, and K. Ko,'Tninski,"Combinational Profiles of Sequential Benchmark Circuits," ISCAS'89, May 1989.
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CITED BY 9
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Sybille Hellebrand , Birgit Reeb , Steffen Tarnick , Hans-Joachim Wunderlich, Pattern generation for a deterministic BIST scheme, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.88-94, November 05-09, 1995, San Jose, California, United States
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Seiji Kajihara , Tetsuji Sumioka , Kozo Kinoshita, Test generation for multiple faults based on parallel vector pair analysis, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.436-439, November 07-11, 1993, Santa Clara, California, United States
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