Automatic functional test generation using the extended finite state machine model

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Automatic functional test generation using the extended finite state machine model

Full text

Pdf (702 KB)

Source

Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 86 - 91

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

Kwang Ting Cheng
A. S. Krishnakumar

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 11, Downloads (12 Months): 93, Citation Count: 26

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/157485.164585 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Edward F. Moore, Sequential Machines: Selected Papers, Addison-Wesley Longman Ltd., Essex, UK, 1964
	2	O. Coudert , C. Berthet , J. C. Madre, Verification of synchronous sequential machines based on symbolic execution, Proceedings of the international workshop on Automatic verification methods for finite state systems, p.365-373, February 1990, Grenoble, France
	3	Ralph A. Marlett, EBT: A comprehensive test generation technique for highly sequential circuits, Proceedings of the 15th conference on Design automation, p.335-339, June 19-21, 1978, Las Vegas, Nevada, United States
	4	W.T. ~g, "The BACK Algorithm for Sequential Test Genetatiort," Proc. Int. Conf. Computer Design (ICCD-88), Rye Brook, NY, pp. 66-69 (October 1988).
	5	Thomas Niermann , Janak H. Patel, HITEC: a test generation package for sequential circuits, Proceedings of the conference on European design automation, February 25-28, 1991, Amsterdam, The Netherlands
	6	T. P. Kelsey and K. K. Saluja, "Fast Test Generation For Sequential Circuits," Proc. Int~l Conf. Computer-Aided Design, pp. 354-357 (Nov. 1989).
	7	Kwang-Ting Cheng , Vishwani D. Agrawal, Unified Methods for VLSI Simulation and Test Generation, Kluwer Academic Publishers, Norwell, MA, 1989
	8	H-K. T. Ma, S. Devadas, A. R. Newton, and A. Sangiovamd-Vincentelli, "Test Generation for Sequential Circuits," IEEE Trans. on Computer-Aided Design, pp. 1081-1093 (October 1988).
	9	A. Ghosh, S. Devadas, and A. R. Newton, "Test Generation and Verification for Highly Sequential Circuits," IEEE Trans. on Computer-Aided Design, pp. 652-667 (May 1991).
	10	I. Pomeranz and S. M. Reddy, "Test Generation for Synchronous Sequential Circuits Using Multiple Observation Times," Fault-Tolerant Computing Symp. (June 1991).
	11	Hyunwoo Cho , Gary D. Hachtel , Fabio Somenzi, Fast Sequential ATPG Based on Implicit State Enumeration, Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner, p.67-74, October 26-30, 1991
	12	K.-T. Cheng, "Recent Advances in Sequential Test Generafion," IEEE VLSI Test Symposium, pp. 241-246 (April 1992).
	13	J-Y. Jou, S. Rothweiler, R. Ernst, S. Sutarwala, and A. Prabhu, "BESTMAP: Behavioral Synthesis from C," International Workshop on Logic Synthesis, Research Triangle Park, North Carolina (May 1989).
	14	Srinivas Devadas , Kurt Keutzer , A. S. Krishnakumar, Design Verfication and Reachability Analysis Using Algebraic Manipulation, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.250-258, October 14-16, 1991
	15	David Lee , Mihalis Yannakakis, Online minimization of transition systems (extended abstract), Proceedings of the twenty-fourth annual ACM symposium on Theory of computing, p.264-274, May 04-06, 1992, Victoria, British Columbia, Canada [doi>10.1145/129712.129738]
	16	"IEEE Standard VHDL Language Reference Manual," IEEE standard, pp. 107 6-1987.
	17	Karl S. Brace , Richard L. Rudell , Randal E. Bryant, Efficient implementation of a BDD package, Proceedings of the 27th ACM/IEEE conference on Design automation, p.40-45, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123222]

CITED BY 26

	Dinos Moundanos , Jacob A. Abraham, On Design Validation Using Verification Technology, Journal of Electronic Testing: Theory and Applications, v.15 n.1-2, p.173-189, August-October 1999
	Farzan Fallah , Srinivas Devadas , Kurt Keutzer, OCCOM: efficient computation of observability-based code coverage metrics for functional verification, Proceedings of the 35th annual conference on Design automation, p.152-157, June 15-19, 1998, San Francisco, California, United States
	Gregor V. Bochmann , Alexandre Petrenko, Protocol testing: review of methods and relevance for software testing, Proceedings of the 1994 ACM SIGSOFT international symposium on Software testing and analysis, p.109-124, August 17-19, 1994, Seattle, Washington, United States
	Aarti Gupta , Sharad Malik , Pranav Ashar, Toward formalizing a validation methodology using simulation coverage, Proceedings of the 34th annual conference on Design automation, p.740-745, June 09-13, 1997, Anaheim, California, United States
	Yatin Hoskote , Timothy Kam , Pei-Hsin Ho , Xudong Zhao, Coverage estimation for symbolic model checking, Proceedings of the 36th ACM/IEEE conference on Design automation, p.300-305, June 21-25, 1999, New Orleans, Louisiana, United States
	Farzan Fallah , Srinivas Devadas , Kurt Keutzer, Functional vector generation for HDL models using linear programming and 3-satisfiability, Proceedings of the 35th annual conference on Design automation, p.528-533, June 15-19, 1998, San Francisco, California, United States
	Yunjian Jiang , Robert K. Brayton, Software synthesis from synchronous specifications using logic simulation techniques, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Farzan Fallah , Pranav Ashar , Srinivas Devadas, Simulation vector generation from HDL descriptions for observability-enhanced statement coverage, Proceedings of the 36th ACM/IEEE conference on Design automation, p.666-671, June 21-25, 1999, New Orleans, Louisiana, United States
	Shi-Yu Huang, On speeding up extended finite state machines using catalyst circuitry, Proceedings of the 2001 conference on Asia South Pacific design automation, p.583-588, January 2001, Yokohama, Japan
	A. S. Krishnakumar , Kwang-Ting Cheng, On the computation of the set of reachable states of hybrid models, Proceedings of the 31st annual conference on Design automation, p.615-620, June 06-10, 1994, San Diego, California, United States
	Chien-Nan Jimmy Liu , I-Ling Chen , Jing-Yang Jou, A Design-for-Verification Technique for Functional Pattern Reduction, IEEE Design & Test, v.20 n.2, p.48-55, March 2003
	Franco Fummi , Donatella Sciuto , Micaela Serra, Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal, IEEE Transactions on Computers, v.48 n.12, p.1305-1323, December 1999
	Alexandre Petrenko , Sergiy Boroday , Roland Groz, Confirming Configurations in EFSM Testing, IEEE Transactions on Software Engineering, v.30 n.1, p.29-42, January 2004
	Ian G. Harris, Fault Models and Test Generation for Hardware-Software Covalidation, IEEE Design & Test, v.20 n.04, p.40-47, January 2003
	Boris Vaysburg , Luay H. Tahat , Bogdan Korel, Dependence analysis in reduction of requirement based test suites, ACM SIGSOFT Software Engineering Notes, v.27 n.4, July 2002
	Yunjian Jiang , Robert K. Brayton, Don't cares in logic minimization of extended finite state machines, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Dinos Moundanos , Jacob A. Abraham , Yatin V. Hoskote, Abstraction Techniques for Validation Coverage Analysis and Test Generation, IEEE Transactions on Computers, v.47 n.1, p.2-14, January 1998
	Florentin Ipate, Testing against a non-controllable stream X-machine using state counting, Theoretical Computer Science, v.353 n.1, p.291-316, 14 March 2006
	Hana Chockler , Orna Kupferman , Moshe Y. Vardi, Coverage metrics for temporal logic model checking, Formal Methods in System Design, v.28 n.3, p.189-212, May 2006
	Ta-Chung Chang , Vikram Iyengar , Elizabeth M. Rudnick, A Biased Random Instruction Generation Environmentfor Architectural Verification of Pipelined Processors, Journal of Electronic Testing: Theory and Applications, v.16 n.1-2, p.13-27, Feb/April 2000
	Yiorgos Makris , Alex Orailoǧlu, RTL Test Justification and Propagation Analysis for Modular Designs, Journal of Electronic Testing: Theory and Applications, v.13 n.2, p.105-120, Oct. 1998
	Chien-Nan Jimmy Liu , I-Ling Chen , Jing-Yang Jou, An efficient design-for-verification technique for HDLs, Proceedings of the 2001 conference on Asia South Pacific design automation, p.103-108, January 2001, Yokohama, Japan
	Florentin Ipate , Mike Holcombe, Complete Testing from a Stream X-Machine Specification, Fundamenta Informaticae, v.64 n.1-4, p.205-216, January 2005
	Bogdan Korel , George Koutsogiannakis , Luay H. Tahat, Model-based test prioritization heuristic methods and their evaluation, Proceedings of the 3rd international workshop on Advances in model-based testing, p.34-43, July 09-12, 2007, London, United Kingdom
	Florentin Ipate , Marian Gheorghe, Testing Non-deterministic Stream X-machine Models and P systems, Electronic Notes in Theoretical Computer Science (ENTCS), 227, p.113-126, January, 2009
	Xinming Wang , S. C. Cheung , W. K. Chan , Zhenyu Zhang, Taming coincidental correctness: Coverage refinement with context patterns to improve fault localization, Proceedings of the 2009 IEEE 31st International Conference on Software Engineering, p.45-55, May 16-24, 2009