Technology mapping for lower power

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Technology mapping for lower power

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 74 - 79

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

Vivek Tiwari
Pranav Ashar
Sharad Malik

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 13, Citation Count: 33

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 33

	Primal Buch , Christopher K. Lennard , A. Richard Newton, Engineering change for power optimization using global sensitivity and synthesis flexibility, Proceedings of the 1997 international symposium on Low power electronics and design, p.88-91, August 18-20, 1997, Monterey, California, United States
	Sue-Hong Chow , Yi-Cheng Ho , TingTing Hwang , C. L. Liu, Low power realization of finite state machines—a decomposition approach, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.3, p.315-340, July 1996
	Huzefa Mehta , Robert Michael Owens , Mary Jane Irwin , Rita Chen , Debashree Ghosh, Techniques for low energy software, Proceedings of the 1997 international symposium on Low power electronics and design, p.72-75, August 18-20, 1997, Monterey, California, United States
	P. Girard , C. Landrault , S. Pravossoudovitch , D. Severac, A gate resizing technique for high reduction in power consumption, Proceedings of the 1997 international symposium on Low power electronics and design, p.281-286, August 18-20, 1997, Monterey, California, United States
	Massoud Pedram, Power minimization in IC design: principles and applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.1, p.3-56, Jan. 1996
	Hai Zhou , D. F. Wong, Optimal low powerX OR gate decomposition, Proceedings of the 37th conference on Design automation, p.104-107, June 05-09, 2000, Los Angeles, California, United States
	S. C. Prasad , K. Roy, Transistor reordering for power minimization under delay constraint, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.2, p.280-300, April 1996
	Unni Narayanan , Hon Wai Leong , Ki-seok Chung , C. L. Liu, Low power multiplexer decomposition, Proceedings of the 1997 international symposium on Low power electronics and design, p.269-274, August 18-20, 1997, Monterey, California, United States
	Daehong Kim , Kiyoung Choi, Power-conscious high level synthesis using loop folding, Proceedings of the 34th annual conference on Design automation, p.441-445, June 09-13, 1997, Anaheim, California, United States
	R. Bahar , M. Burns , G. Hachtel , E. Macii , H. Shin , F. Somenzi, Symbolic computation of logic implications for technology-dependent low-power synthesis, Proceedings of the 1996 international symposium on Low power electronics and design, p.163-168, August 12-14, 1996, Monterey, California, United States
	Chau-Shen Chen , TingTing Hwang , C. L. Liu, Low power FPGA design—a re-engineering approach, Proceedings of the 34th annual conference on Design automation, p.656-661, June 09-13, 1997, Anaheim, California, United States
	Olivier Coudert , Ramsey Haddad, Integrated resynthesis for low power, Proceedings of the 1996 international symposium on Low power electronics and design, p.169-174, August 12-14, 1996, Monterey, California, United States
	Vivek Tiwari , Deo Singh , Suresh Rajgopal , Gaurav Mehta , Rakesh Patel , Franklin Baez, Reducing power in high-performance microprocessors, Proceedings of the 35th annual conference on Design automation, p.732-737, June 15-19, 1998, San Francisco, California, United States
	R. Iris Bahar , Ernest T. Lampe , Enrico Macii, Power optimization of technology-dependent circuits based on symbolic computation of logic implications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.3, p.267-293, July 2000
	Vivek Tiwari , Sharad Malik , Pranav Ashar, Guarded evaluation: pushing power management to logic synthesis/design, Proceedings of the 1995 international symposium on Low power design, p.221-226, April 23-26, 1995, Dana Point, California, United States
	Jan-Min Hwang , Feng-Yi Chiang , TingTing Hwang, A re-engineering approach to low power FPGA design using SPFD, Proceedings of the 35th annual conference on Design automation, p.722-725, June 15-19, 1998, San Francisco, California, United States
	Unni Narayanan , C. L. Liu, Low power logic synthesis for XOR based circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.570-574, November 09-13, 1997, San Jose, California, United States
	Chi-Ying Tsui , Massoud Pedram , Alvin M. Despain, Efficient estimation of dynamic power consumption under a real delay model, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.224-228, November 07-11, 1993, Santa Clara, California, United States
	Christopher K. Lennard , A. Richard Newton, An estimation technique to guide low power resynthesis algorithms, Proceedings of the 1995 international symposium on Low power design, p.227-232, April 23-26, 1995, Dana Point, California, United States
	Hai Zhou , D. F. Wong, An exact gate decomposition algorithm for low-power technology mapping, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.575-580, November 09-13, 1997, San Jose, California, United States
	S. Gavrilov , A. Glebov , S. Pullela , S. C. Moore , A. Dharchoudhury , R. Panda , G. Vijayan , D. T. Blaauw, Library-less synthesis for static CMOS combinational logic circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.658-662, November 09-13, 1997, San Jose, California, United States
	R. Iris Bahar , Fabio Somenzi, Boolean techniques for low power driven re-synthesis, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.428-432, November 05-09, 1995, San Jose, California, United States
	Sumit Roy , Krishna Belkhale , Prithviraj Banerjee, An &agr;-approxmimate algorithm for delay-constraint technology mapping, Proceedings of the 36th ACM/IEEE conference on Design automation, p.367-372, June 21-25, 1999, New Orleans, Louisiana, United States
	Bernhard Rohfleisch , Alfred Kölbl , Bernd Wurth, Reducing power dissipation after technology mapping by structural transformations, Proceedings of the 33rd annual conference on Design automation, p.789-794, June 03-07, 1996, Las Vegas, Nevada, United States
	Amir H. Farrahi , Gustavo E. Téllez , Majid Sarrafzadeh, Memory segmentation to exploit sleep mode operation, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.36-41, June 12-16, 1995, San Francisco, California, United States
	Amir H. Farrahi , Majid Sarrafzadeh, System partitioning to maximize sleep time, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.452-455, November 05-09, 1995, San Jose, California, United States
	Srinivas Devadas , Sharad Malik, A survey of optimization techniques targeting low power VLSI circuits, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.242-247, June 12-16, 1995, San Francisco, California, United States
	R. Iris Bahar , Gary D. Hachtel , Enrico Macii , Fabio Somenzi, A symbolic method to reduce power consumption of circuits containing false paths, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.368-371, November 06-10, 1994, San Jose, California, United States
	Jo Dale Carothers , Radjakichenin Radjassamy, Low Power VLSI Design Techniques - The Current State, Integrated Computer-Aided Engineering, v.5 n.2, p.153-176, April 1998
	Rajeev Murgai , Masahiro Fujita, On reducing transitions through data modifications, Proceedings of the conference on Design, automation and test in Europe, p.19-es, January 1999, Munich, Germany
	Zile Wei , Donald Chai , A. Richard Newton , Andreas Kuehlmann, Fast Boolean Matching with Don't Cares, Proceedings of the 7th International Symposium on Quality Electronic Design, p.346-351, March 27-29, 2006
	R. Murgai , R. K. Brayton , A. Sangiovanni-Vincentelli, Decomposition of logic functions for minimum transition activity, Proceedings of the 1995 European conference on Design and Test, p.404, March 06-09, 1995
	S. Gavrilov , A. Glebov , S. Rusakov , D. Blaauw , L. Jones , G. Vijayan, Fast power loss calculation for digital static CMOS circuits, Proceedings of the 1997 European conference on Design and Test, p.411, March 17-20, 1997