Technology decomposition and mapping targeting low power dissipation

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Technology decomposition and mapping targeting low power dissipation

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 68 - 73

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

Chi-Ying Tsui
Massoud Pedram
Alvin M. Despain

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 35, Citation Count: 51

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	12	C. Y. Tsui, M. Pedram, and A. Despain. Technology decomposition and mapping targeting low power dissipation. Technical Report CNEG 92-16, Electrical Engineering-System Department, University of Southern California, October 1992.

CITED BY 51

	Aurobindo Dasgupta , Ramesh Karri, Simultaneous scheduling and binding for power minimization during microarchitecture synthesis, Proceedings of the 1995 international symposium on Low power design, p.69-74, April 23-26, 1995, Dana Point, California, United States
	Primal Buch , Christopher K. Lennard , A. Richard Newton, Engineering change for power optimization using global sensitivity and synthesis flexibility, Proceedings of the 1997 international symposium on Low power electronics and design, p.88-91, August 18-20, 1997, Monterey, California, United States
	Sasan Iman , Massoud Pedram , Kamal Chaudhary, Technology mapping using fuzzy logic, Proceedings of the 31st annual conference on Design automation, p.333-338, June 06-10, 1994, San Diego, California, United States
	Sue-Hong Chow , Yi-Cheng Ho , TingTing Hwang , C. L. Liu, Low power realization of finite state machines—a decomposition approach, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.3, p.315-340, July 1996
	Tan-Li Chou , Kaushik Roy , Sharat Prasad, Estimation of circuit activity considering signal correlations and simultaneous switching, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.300-303, November 06-10, 1994, San Jose, California, United States
	Hai Zhou , D. F. Wong, An exact gate decomposition algorithm for low-power technology mapping, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.575-580, November 09-13, 1997, San Jose, California, United States
	Sasan Iman , Massoud Pedram, Logic extraction and factorization for low power, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.248-253, June 12-16, 1995, San Francisco, California, United States
	Hai Zhou , D. F. Wong, Optimal low powerX OR gate decomposition, Proceedings of the 37th conference on Design automation, p.104-107, June 05-09, 2000, Los Angeles, California, United States
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	Chi-Ying Tsui , Massoud Pedram , Alvin M. Despain, Efficient estimation of dynamic power consumption under a real delay model, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.224-228, November 07-11, 1993, Santa Clara, California, United States
	Daehong Kim , Kiyoung Choi, Power-conscious high level synthesis using loop folding, Proceedings of the 34th annual conference on Design automation, p.441-445, June 09-13, 1997, Anaheim, California, United States
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	Yu-Lung Hsu , Sying-Jyan Wang, Retiming-based logic synthesis for low-power, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
	Kimiyoshi Usami , Mutsunori Igarashi, Low-power design methodology and applications utilizing dual supply voltages, Proceedings of the 2000 conference on Asia South Pacific design automation, p.123-128, January 2000, Yokohama, Japan
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	R. Iris Bahar , Fabio Somenzi, Boolean techniques for low power driven re-synthesis, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.428-432, November 05-09, 1995, San Jose, California, United States
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	Chingren Lee , Jenq Kuen Lee , Tingting Hwang , Shi-Chun Tsai, Compiler optimization on VLIW instruction scheduling for low power, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.8 n.2, p.252-268, April 2003
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	Luca Benini , Polly Siegel , Giovanni De Micheli, Saving Power by Synthesizing Gated Clocks for Sequential Circuits, IEEE Design & Test, v.11 n.4, p.32-41, October 1994
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	Chang-woo Kang , Massoud Pedram, Technology mapping for low leakage power and high speed with hot-carrier effect consideration, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Chang Woo Kang , Massoud Pedram, Low-power clustering with minimum logic replication for coarse-grained, antifuse based FPGAs, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA
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