Technology decomposition and mapping targeting low power dissipation

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Technology decomposition and mapping targeting low power dissipation

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 68 - 73

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

Chi-Ying Tsui
Massoud Pedram
Alvin M. Despain

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 9, Downloads (12 Months): 41, Citation Count: 51

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	R. K. Brayton, G. D. Hachtel, and A. L. Sangiovanni- Vincentelll. Multilevel logic synthesis. In Proceedings of the IEEE, volume 78, pages 264-300, February 1990.
	2	Richard Burch , Farid Najm , Ping Yang , Dale Hocevar, Pattern-independent current estimation for reliability analysis of CMOS circuits, Proceedings of the 25th ACM/IEEE conference on Design automation, p.294-299, June 12-15, 1988, Atlantic City, New Jersey, United States
	3	K. Chaudhary , M. Pedram, A near optimal algorithm for technology mapping minimizing area under delay constraints, Proceedings of the 29th ACM/IEEE conference on Design automation, p.492-498, June 08-12, 1992, Anaheim, California, United States
	4	M. A. Cirit. Estimating dynamic power consumption of CMOS circuits. In Proceedings of the IEEE International Conference on Computer Aided Design, pages 534-537, November 1987.
	5	E. Detjens, G. Gannot, R. Rudell, A. Sangiovanni- Vincentelli, and A. Wang. Technology mapping in MIS. In Proceedings of the IEEE International Conference on Computer Aided Design, pages 116-119, November 1987.
	6	A. Ghosh , S. Devadas , K. Keutzer , J. White, Estimation of average switching activity in combinational and sequential circuits, Proceedings of the 29th ACM/IEEE conference on Design automation, p.253-259, June 08-12, 1992, Anaheim, California, United States
	7	D. A. Huffman. A method for the construction of minimum redundancy codes. In Proceedings of the IRE, volume 40, pages 1098-1101, September 1952.
	8	D.S. Parker Jr. Conditions for optimality of the Huffman algorithm. SIAM Journal o.f Computing, 9(3):470-489, August 1980.
	9	Lawrence L. Larmore , Daniel S. Hirschberg, A fast algorithm for optimal length-limited Huffman codes, Journal of the ACM (JACM), v.37 n.3, p.464-473, July 1990 [doi>10.1145/79147.79150]
	10	Farid N. Najm, Transition density, a stochastic measure of activity in digital circuits, Proceedings of the 28th conference on ACM/IEEE design automation, p.644-649, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127744]
	11	Amelia Shen , Abhijit Ghosh , Srinivas Devadas , Kurt Keutzer, On average power dissipation and random pattern testability of CMOS combinational logic networks, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.402-407, November 1992, Santa Clara, California, United States
	12	C. Y. Tsui, M. Pedram, and A. Despain. Technology decomposition and mapping targeting low power dissipation. Technical Report CNEG 92-16, Electrical Engineering-System Department, University of Southern California, October 1992.

CITED BY 51

	Aurobindo Dasgupta , Ramesh Karri, Simultaneous scheduling and binding for power minimization during microarchitecture synthesis, Proceedings of the 1995 international symposium on Low power design, p.69-74, April 23-26, 1995, Dana Point, California, United States
	Primal Buch , Christopher K. Lennard , A. Richard Newton, Engineering change for power optimization using global sensitivity and synthesis flexibility, Proceedings of the 1997 international symposium on Low power electronics and design, p.88-91, August 18-20, 1997, Monterey, California, United States
	Sasan Iman , Massoud Pedram , Kamal Chaudhary, Technology mapping using fuzzy logic, Proceedings of the 31st annual conference on Design automation, p.333-338, June 06-10, 1994, San Diego, California, United States
	Sue-Hong Chow , Yi-Cheng Ho , TingTing Hwang , C. L. Liu, Low power realization of finite state machines—a decomposition approach, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.3, p.315-340, July 1996
	Tan-Li Chou , Kaushik Roy , Sharat Prasad, Estimation of circuit activity considering signal correlations and simultaneous switching, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.300-303, November 06-10, 1994, San Jose, California, United States
	Hai Zhou , D. F. Wong, An exact gate decomposition algorithm for low-power technology mapping, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.575-580, November 09-13, 1997, San Jose, California, United States
	Sasan Iman , Massoud Pedram, Logic extraction and factorization for low power, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.248-253, June 12-16, 1995, San Francisco, California, United States
	Hai Zhou , D. F. Wong, Optimal low powerX OR gate decomposition, Proceedings of the 37th conference on Design automation, p.104-107, June 05-09, 2000, Los Angeles, California, United States
	S. C. Prasad , K. Roy, Transistor reordering for power minimization under delay constraint, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.2, p.280-300, April 1996
	Unni Narayanan , Hon Wai Leong , Ki-seok Chung , C. L. Liu, Low power multiplexer decomposition, Proceedings of the 1997 international symposium on Low power electronics and design, p.269-274, August 18-20, 1997, Monterey, California, United States
	Massoud Pedram, Power minimization in IC design: principles and applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.1, p.3-56, Jan. 1996
	R. Bahar , M. Burns , G. Hachtel , E. Macii , H. Shin , F. Somenzi, Symbolic computation of logic implications for technology-dependent low-power synthesis, Proceedings of the 1996 international symposium on Low power electronics and design, p.163-168, August 12-14, 1996, Monterey, California, United States
	Amir H. Farrahi , Gustavo E. Téllez , Majid Sarrafzadeh, Memory segmentation to exploit sleep mode operation, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.36-41, June 12-16, 1995, San Francisco, California, United States
	Olivier Coudert , Ramsey Haddad, Integrated resynthesis for low power, Proceedings of the 1996 international symposium on Low power electronics and design, p.169-174, August 12-14, 1996, Monterey, California, United States
	R. Iris Bahar , Ernest T. Lampe , Enrico Macii, Power optimization of technology-dependent circuits based on symbolic computation of logic implications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.3, p.267-293, July 2000
	Luca Benini , Giovanni De Micheli, Transformation and synthesis of FSMs for low-power gated-clock implementation, Proceedings of the 1995 international symposium on Low power design, p.21-26, April 23-26, 1995, Dana Point, California, United States
	Leon Stok , Vivek Tiwari, Technology mapping, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Unni Narayanan , C. L. Liu, Low power logic synthesis for XOR based circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.570-574, November 09-13, 1997, San Jose, California, United States
	Michael J. Alexander, Power optimization for FPGA look-up tables, Proceedings of the 1997 international symposium on Physical design, p.156-162, April 14-16, 1997, Napa Valley, California, United States
	Chingren Lee , Jenq Kuen Lee , TingTing Hwang , Shi-Chun Tsai, Compiler optimization on instruction scheduling for low power, Proceedings of the 13th international symposium on System synthesis, September 20-22, 2000, Madrid, Spain
	Masako Murofushi , Takashi Ishioka , Masami Murakata , Takashi Mitsuhashi, Layout driven re-synthesis for low power consumption LSIs, Proceedings of the 34th annual conference on Design automation, p.666-669, June 09-13, 1997, Anaheim, California, United States
	Vivek Tiwari , Deo Singh , Suresh Rajgopal , Gaurav Mehta , Rakesh Patel , Franklin Baez, Reducing power in high-performance microprocessors, Proceedings of the 35th annual conference on Design automation, p.732-737, June 15-19, 1998, San Francisco, California, United States
	Chi-Ying Tsui , Massoud Pedram , Alvin M. Despain, Efficient estimation of dynamic power consumption under a real delay model, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.224-228, November 07-11, 1993, Santa Clara, California, United States
	Daehong Kim , Kiyoung Choi, Power-conscious high level synthesis using loop folding, Proceedings of the 34th annual conference on Design automation, p.441-445, June 09-13, 1997, Anaheim, California, United States
	Qi Wang , Sarma B. K. Vrudhula , Gary Yeap , Shantanu Ganguly, Power reduction and power-delay trade-offs using logic transformations, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.4 n.1, p.97-121, Jan. 1999
	Peter H. Schneider , Kurt J. Antreich , Ulf Schlichtmann, A new power estimation technique with application to decomposition of Boolean functions for low power, Proceedings of the conference on European design automation, p.388-393, September 19-23, 1994, Grenoble, France
	De-Sheng Chen , Majid Sarrafzadeh, An exact algorithm for low power library-specific gate re-sizing, Proceedings of the 33rd annual conference on Design automation, p.783-788, June 03-07, 1996, Las Vegas, Nevada, United States
	Christopher K. Lennard , A. Richard Newton, An estimation technique to guide low power resynthesis algorithms, Proceedings of the 1995 international symposium on Low power design, p.227-232, April 23-26, 1995, Dana Point, California, United States
	Junghwan Choi , Jinhwan Jeon , Kiyoung Choi, Power minimization of functional units partially guarded computation, Proceedings of the 2000 international symposium on Low power electronics and design, p.131-136, July 25-27, 2000, Rapallo, Italy
	Yu-Lung Hsu , Sying-Jyan Wang, Retiming-based logic synthesis for low-power, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
	Kimiyoshi Usami , Mutsunori Igarashi, Low-power design methodology and applications utilizing dual supply voltages, Proceedings of the 2000 conference on Asia South Pacific design automation, p.123-128, January 2000, Yokohama, Japan
	S. Gavrilov , A. Glebov , S. Pullela , S. C. Moore , A. Dharchoudhury , R. Panda , G. Vijayan , D. T. Blaauw, Library-less synthesis for static CMOS combinational logic circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.658-662, November 09-13, 1997, San Jose, California, United States
	Sumit Roy , Krishna Belkhale , Prithviraj Banerjee, An &agr;-approxmimate algorithm for delay-constraint technology mapping, Proceedings of the 36th ACM/IEEE conference on Design automation, p.367-372, June 21-25, 1999, New Orleans, Louisiana, United States
	R. Iris Bahar , Fabio Somenzi, Boolean techniques for low power driven re-synthesis, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.428-432, November 05-09, 1995, San Jose, California, United States
	Amir H. Farrahi , Majid Sarrafzadeh, System partitioning to maximize sleep time, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.452-455, November 05-09, 1995, San Jose, California, United States
	R. Iris Bahar , Gary D. Hachtel , Enrico Macii , Fabio Somenzi, A symbolic method to reduce power consumption of circuits containing false paths, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.368-371, November 06-10, 1994, San Jose, California, United States
	Srinivas Devadas , Sharad Malik, A survey of optimization techniques targeting low power VLSI circuits, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.242-247, June 12-16, 1995, San Francisco, California, United States
	Qi Wang , Sarma B. K. Vrudhula, Multi-level logic optimization for low power using local logic transformations, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.270-277, November 10-14, 1996, San Jose, California, United States
	Chingren Lee , Jenq Kuen Lee , Tingting Hwang , Shi-Chun Tsai, Compiler optimization on VLIW instruction scheduling for low power, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.8 n.2, p.252-268, April 2003
	Ki-Wook Kim , Taewhan Kim , Ting-Ting Hwang , Sung-Mo Kang , C. L. Liu, Logic transformation for low-power synthesis, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.7 n.2, p.265-283, April 2002
	Winfried Nöth , Reiner Kolla, Node normalization and decomposition in low power technology mapping, Proceedings of the 1997 international symposium on Low power electronics and design, p.275-280, August 18-20, 1997, Monterey, California, United States
	Luca Benini , Polly Siegel , Giovanni De Micheli, Saving Power by Synthesizing Gated Clocks for Sequential Circuits, IEEE Design & Test, v.11 n.4, p.32-41, October 1994
	Yi-Ping You , Chingren Lee , Jenq Kuen Lee, Compilers for leakage power reduction, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.1, p.147-164, January 2006
	Chang-woo Kang , Massoud Pedram, Technology mapping for low leakage power and high speed with hot-carrier effect consideration, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Chang Woo Kang , Massoud Pedram, Low-power clustering with minimum logic replication for coarse-grained, antifuse based FPGAs, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA
	Zili Shao , Qingfeng Zhuge , Meilin Liu , Chun Xue , Edwin H. M. Sha , Bin Xiao, Algorithms and analysis of scheduling for loops with minimum switching, International Journal of Computational Science and Engineering, v.2 n.1/2, p.88-97, June 2006
	Jo Dale Carothers , Radjakichenin Radjassamy, Low Power VLSI Design Techniques - The Current State, Integrated Computer-Aided Engineering, v.5 n.2, p.153-176, April 1998
	Ki-Wook Kim , TingTing Hwang , C. L. Liu , Sung-Mo Kang, Logic transformation for low power synthesis, Proceedings of the conference on Design, automation and test in Europe, p.35-es, January 1999, Munich, Germany
	R. Murgai , R. K. Brayton , A. Sangiovanni-Vincentelli, Decomposition of logic functions for minimum transition activity, Proceedings of the 1995 European conference on Design and Test, p.404, March 06-09, 1995
	S. Gavrilov , A. Glebov , S. Rusakov , D. Blaauw , L. Jones , G. Vijayan, Fast power loss calculation for digital static CMOS circuits, Proceedings of the 1997 European conference on Design and Test, p.411, March 17-20, 1997
	Ashok K. Murugavel , N. Ranganathan, A Real Delay Switching Activity Simulator based on Petri net Modeling, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.181, January 07-11, 2002