Automatic technology mapping for generalized fundamental-mode asynchronous designs

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Automatic technology mapping for generalized fundamental-mode asynchronous designs

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 61 - 67

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

Polly Siegel
Giovanni De Micheli
David Dill

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 12, Downloads (12 Months): 25, Citation Count: 10

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	2	Kenneth Y. Yun , David L. Dill, Automatic synthesis of 3D asynchronous state machines, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.576-580, November 1992, Santa Clara, California, United States
	3	Al Davis , Bill Coates , Ken Stevens, Automatic Synthesis of Fast Compact Asynchronous Control Circuits, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, p.193-207, March 31-April 02, 1993
	4	K. Keutzer, DAGON: technology binding and local optimization by DAG matching, Proceedings of the 24th ACM/IEEE conference on Design automation, p.341-347, June 28-July 01, 1987, Miami Beach, Florida, United States [doi>10.1145/37888.37940]
	5	Richard L. Rudell , Alberto Sangiovanni-Vincentelli, Logic synthesis for vlsi design, 1989
	6	F. Mailhot, "Algorithms for technology mapping based on binary decision diagrams and on boolean operations," IEEE Transactions on CAD/ICAS, in press.
	7	Edward J. McCluskey, Logic design principles with emphasis on testable semicustom circuits, Prentice-Hall, Inc., Upper Saddle River, NJ, 1986
	8	E. B. Eichelberger, "Hazard detection in combinational and sequential switching circuits," IBM Journal, Mar. 1965.
	9	J. Bredeson, "Synthesis of multiple input change hazard-free combinational switching circuilLs without feedback," international Journal of Electronics, vol. 39, no. 6, pp. 615-624, Dec. 1975.
	10	R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. R. Wang, "MIS" A multiple-level logic optimization system," IEEE Transactions on CAD/ICAS, vol. 6, no. 6, pp. 1062-1081, Nov. 1987.
	11	Steven M. Nowick , David L. Dill, Exact two-level minimization of hazard-free logic with multiple-input changes, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.626-630, November 1992, Santa Clara, California, United States
	12	Stephen H. Unger, Asynchronous Sequential Switching Circuit, Krieger Publishing Co., Inc., Melbourne, FL, 1983
	13	Polly Siegel , Giovanni DeMicheli , David Dill, Automatic Technology Mapping for Generalized Fundamental-Mode Asynchronous Designs, Stanford University, Stanford, CA, 1993
	14	D. V. Heinbuch, CMOS3 Cell Library. Addison-Wesley, 1987.
	15	J. Beister, "A unified approach to combinational hazards," IEEE Transactions on Computel.s, vol. 23, no. 6, pp. 566-575, June 1974.
	16	R. Rudell and A. Sangiovanni-Vincentelli, "Multiple-valued minimization for PLA optimization," IEEE Transactions on CA D/ICA S, Sept. 1987.
	17	J. Bredeson and P. Hulina, "Elimination of static and dynamic hazards for multiple input changes in combinational switching circuits," Information and Control, vol. 20, no. 2, pp. 114-124, Mar. 1972.
	18	S. M. Nowick, K. Yun, and D. L. Dill, "Practical asynchronous controller design," in International Conference on Computer Design, IEEE Computer Society Press, 1992.

CITED BY 10

	P. Beerel , W. Chou , K. Yun, A heuristic covering technique for optimizing average-case delay in the technology mapping of asynchronous burst-mode circuits, Proceedings of the conference on European design automation, p.284-289, September 1996, Geneva, Switzerland
	Kenneth Y. Yun , David L. Dill, Unifying synchronous/asynchronous state machine synthesis, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.255-260, November 07-11, 1993, Santa Clara, California, United States
	Jordi Cortadella , Michael Kishinevsky , Alex Kondratyev , Luciano Lavagno , Enric Pastor , Alex Yakovlev, Decomposition and technology mapping of speed-independent circuits using Boolean relations, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.220-227, November 09-13, 1997, San Jose, California, United States
	Luciano Lavagno , Steven M. Nowick, Asynchronous control circuits, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Robert M. Fuhrer , Bill Lin , Steven M. Nowick, Symbolic hazard-free minimization and encoding of asynchronous finite state machines, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.604-611, November 05-09, 1995, San Jose, California, United States
	Erik Brunvand , Steven Nowick , Kenneth Yun, Practical advances in asynchronous design and in asynchronous/synchronous interfaces, Proceedings of the 36th ACM/IEEE conference on Design automation, p.104-109, June 21-25, 1999, New Orleans, Louisiana, United States
	Polly Siegel , Giovanni De Micheli, Decomposition methods for library binding of speed-independent asynchronous designs, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.558-565, November 06-10, 1994, San Jose, California, United States
	Alan Marshall , Polly Siegel , Bill Coates, Designing an Asynchronous Communications Chip, IEEE Design & Test, v.11 n.2, p.8-21, April 1994
	Scott Hauck , Steven Burns , Gaetano Borriello , Carl Ebeling, An FPGA for Implementing Asynchronous Circuits, IEEE Design & Test, v.11 n.3, p.60-69, July 1994
	Jordi Cortadella , Michael Kishinevsky , Alex Kondratyev , Luciano Lavagno , Alex Yakovlev, Technology Mapping of Speed-Independent Circuits Based on Combinational Decomposition and Resynthesis, Proceedings of the 1997 European conference on Design and Test, p.98, March 17-20, 1997