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 REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Kevin Bolding and Lawrence Snyder. Mesh and Torus Chaotic Routing. In Proceedings of the Brown/MIT Conference on Advanced Research in VLSI and Parallel Systems, March 1992.
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C. Ebeling and O. Zajicek. Validating VLSI Circuit Layout by Wirelist Comparison. In Proceedings of the Conference on Computer Aided Design (ICCAD), pages 172-173, 1983.
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Carl Ebeling. GeminiII: A Second Generation Layout Validation Tool. In Proceedings of the Conference on Computer Aided Design (ICCAD), pages 322-325, November 1988.
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F. Luellau , T. Hoepken , E. Barke, A technology independent block extraction algorithm, Proceedings of the 21st conference on Design automation, p.610-615, June 25-27, 1984, Albuquerque, New Mexico, United States
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Georg Pelz and UIi Roettcher. Circuit Comparison by Hierarchical Pattern Matching. In Proceedings of the Conference on Computer Aided Design (ICCAD), pages 290-293, 1991.
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T. Watanabe, M. Endo, and N. Miyahara. A New Automatic Logic Interconnection Verification System for VLSI Design. IEEE Transactions on Computer Aided Design, CAD-2:70- 82, April 1983.
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CITED BY 17
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A. R. Conn , I. M. Elfadel , W. W. Molzen, Jr. , P. R. O'Brien , P. N. Strenski , C. Visweswariah , C. B. Whan, Gradient-based optimization of custom circuits using a static-timing formulation, Proceedings of the 36th ACM/IEEE conference on Design automation, p.452-459, June 21-25, 1999, New Orleans, Louisiana, United States
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Andrew B. Kahng , Darko Kirovski , Stefanus Mantik , Miodrag Potkonjak , Jennifer L. Wong, Copy detection for intellectual property protection of VLSI designs, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.600-605, November 07-11, 1999, San Jose, California, United States
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Jennifer L. White , Anthony S. Wojcik , Moon-Jung Chung , Travis E. Doom, Candidate subcircuits for functional module identification in logic circuits, Proceedings of the 10th Great Lakes symposium on VLSI, p.34-38, March 02-04, 2000, Chicago, Illinois, United States
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Pawan Kulshreshtha , Robert Palermo , Mohammad Mortazavi , Cyrus Bamji , Hakan Yalcin, Transistor-level timing analysis using embedded simulation, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
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Adarsh K. Jain , Lin Yuan , Pushkin R. Pari , Gang Qu, Zero overhead watermarking technique for FPGA designs, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 28-29, 2003, Washington, D. C., USA
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Sambuddha Bhattacharya , Nuttorn Jangkrajarng , Roy Hartono , C-J. Richard Shi, Hierarchical extraction and verification of symmetry constraints for analog layout automation, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.400-405, January 27-30, 2004, Yokohama, Japan
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Sambuddha Bhattacharya , Nuttorn Jangkrajarng , Roy Hartono , C.-J. Richard Shi, Correct-by-construction layout-centric retargeting of large analog designs, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
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