Elimination of dynamic hazards by factoring

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Elimination of dynamic hazards by factoring

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international Design Automation Conference table of contents

Dallas, Texas, United States

Pages: 7 - 13

Year of Publication: 1993

ISBN:0-89791-577-1

Authors

Cho W. Moon
Robert K. Brayton

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 8, Downloads (12 Months): 17, Citation Count: 0

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	D. B. Armstrong, A. D. Friedman, and P. R. Menon. "Design of Asynchronous Circuits Assuming Unbounded Gate Delays". IEEE Tran. Computers, C-18(12):1110- 1120, December 1969.
	2	Jon G. Bredeson. "On Multiple Input Change Hazard-Free Combinational Switching Circuits Without Feedback". In 14th Annual Symposium on Switching and Automata Theory, pages 56-63, October 1973.
	3	Jon G. Bredeson and Paul T, Hulina. "Elimination of Static and Dynamic Hazards for Multiple Input Changes in Combinational Switching Circuits". Information and Control, 20:114-124, 1972.
	4	Tam-Anh Chu. "Synthesis of Self-timed VLSI Circuits frorn Graph-theoretic Specifications". PhD thesis, MIT, June 1987.
	5	M. Hack, ANALYSIS OF PRODUCTION SCHEMATA BY PETRI NETS, Massachusetts Institute of Technology, Cambridge, MA, 1972
	6	L. Lavagno, C. W. Moon, R. K. Brayton, and A. Sangiovanni-Vincentelli. "A Novel Framework for Solving the State Assignment Problem for Event-based Specifications". Technical Report UCB/ERL M92/19, UC Berkeley, March 1992.
	7	Cho Woo Moon, Synthesis and verification of asynchronous circuits from graphical specifications, University of California at Berkeley, Berkeley, CA, 1992
	8	Cho W. Moon, Paul R. Stephan, and Robert K. Brayton. "Synthesis of Hazard-free Asynchronous Circuits from Graphical Specifications". In Proc. Int'l. Conf. Computer- Aided Design, 1991.
	9	Cho W. Moon , Paul R. Stephan , Robert K. Brayton, Specification, synthesis, and verification of hazard-free asynchronous circuits, Journal of VLSI Signal Processing Systems, v.7 n.1-2, p.85-100, Feb. 1994 [doi>10.1007/BF02108191]
	10	Tadao Murata. "Petri Nets: Properties, Analysis and Applications". Proceedings of the IEEE, 77(4):541 - 580, April 1989.
	11	Steven M. Nowick , David L. Dill, Exact two-level minimization of hazard-free logic with multiple-input changes, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.626-630, November 1992, Santa Clara, California, United States
	12	Peter Vanbekbergen , Bill Lin , Gert Goosens , Hugo De Man, A generalized state assignment theory for transformation on signal transition graphs, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.112-117, November 1992, Santa Clara, California, United States
	13	Victor I. Varshavsky, editor. Self-Timed Control of Concurrent Processes, volume 52. Kluwer Academic Publishers, 1990. (Russian Edition Published in 1986).