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ABSTRACT
A high-performance resistive bridging fault simulator SUPERB (Simulator Utilizing Parallel Evaluation of Resistive Bridges) is proposed. It is based on fault sectioning in combination with parallel-pattern or parallel-fault multiple-stuck-at simulation. It outperforms a conventional interval-based resistive bridging fault simulator by three orders of magnitude while delivering identical results. Further competing tools are outperformed by several orders of magnitude. Industrial-size circuits, including a multi-million-gates design, could be simulated with runtimes within an order of magnitude of the runtimes for pattern-parallel stuck-at fault simulation.
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INDEX TERMS
Primary Classification:
B.
Hardware
B.1
CONTROL STRUCTURES AND MICROPROGRAMMING
B.1.3
Control Structure Reliability, Testing, and Fault-Tolerance**
Additional Classification:
B.
Hardware
B.2
ARITHMETIC AND LOGIC STRUCTURES
B.2.3
Reliability, Testing, and Fault-Tolerance**
B.7
INTEGRATED CIRCUITS
B.7.2
Design Aids
Subjects:
Simulation
B.8
Performance and Reliability
B.8.1
Reliability, Testing, and Fault-Tolerance
J.
Computer Applications
J.6
COMPUTER-AIDED ENGINEERING
Subjects:
Computer-aided design (CAD)
General Terms:
Algorithms,
Reliability
Keywords:
PPSFP,
Resistive bridging faults,
SPPFP,
bridging fault simulation,
fault mapping
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